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Added English Language description for stwup instruction
[openpower-isa.git]
/
openpower
/
isa
/
pifixedstore.mdwn
diff --git
a/openpower/isa/pifixedstore.mdwn
b/openpower/isa/pifixedstore.mdwn
index a8060e56086da1d1a2716b8cda813d16580c4e5c..8a45cd96858ca026ec0957baa7f2b50ec6c111c9 100644
(file)
--- a/
openpower/isa/pifixedstore.mdwn
+++ b/
openpower/isa/pifixedstore.mdwn
@@
-7,15
+7,25
@@
D-Form
D-Form
-* stbu RS,D(RA)
+* stbu
p
RS,D(RA)
Pseudo-code:
EA <- (RA) + EXTS(D)
ea <- (RA)
Pseudo-code:
EA <- (RA) + EXTS(D)
ea <- (RA)
- MEM(
r
a, 1) <- (RS)[XLEN-8:XLEN-1]
+ MEM(
e
a, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ D.
+ (RS)[56:63] are stored into the byte in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-24,7
+34,7
@@
Special Registers Altered:
X-Form
X-Form
-* stbux RS,RA,RB
+* stbu
p
x RS,RA,RB
Pseudo-code:
Pseudo-code:
@@
-33,6
+43,16
@@
Pseudo-code:
MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
MEM(ea, 1) <- (RS)[XLEN-8:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ (RS)[56:63] are stored into the byte in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-41,7
+61,7
@@
Special Registers Altered:
D-Form
D-Form
-* sthu RS,D(RA)
+* sthu
p
RS,D(RA)
Pseudo-code:
Pseudo-code:
@@
-50,6
+70,12
@@
Pseudo-code:
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA|0)+ D.
+ (RS)[48:63] are stored into the halfword in storage
+ addressed by EA.
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-58,7
+84,7
@@
Special Registers Altered:
X-Form
X-Form
-* sthux RS,RA,RB
+* sthu
p
x RS,RA,RB
Pseudo-code:
Pseudo-code:
@@
-67,6
+93,16
@@
Pseudo-code:
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
MEM(ea, 2) <- (RS)[XLEN-16:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ (RB).
+ (RS)[56:63] are stored into the byte in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-75,7
+111,7
@@
Special Registers Altered:
D-Form
D-Form
-* stwu RS,D(RA)
+* stwu
p
RS,D(RA)
Pseudo-code:
Pseudo-code:
@@
-84,6
+120,16
@@
Pseudo-code:
MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
MEM(ea, 4) <- (RS)[XLEN-32:XLEN-1]
RA <- EA
+Description:
+
+ Let the effective address (EA) be the sum (RA)+ D.
+ (RS)[32:63] are stored into the word in storage addressed
+ by EA.
+
+ EA is placed into register RA.
+
+ If RA=0, the instruction form is invalid.
+
Special Registers Altered:
None
Special Registers Altered:
None
@@
-92,7
+138,7
@@
Special Registers Altered:
X-Form
X-Form
-* stwux RS,RA,RB
+* stwu
p
x RS,RA,RB
Pseudo-code:
Pseudo-code:
@@
-109,7
+155,7
@@
Special Registers Altered:
DS-Form
DS-Form
-* stdu RS,DS(RA)
+* stdu
p
RS,DS(RA)
Pseudo-code:
Pseudo-code:
@@
-126,7
+172,7
@@
Special Registers Altered:
X-Form
X-Form
-* stdux RS,RA,RB
+* stdu
p
x RS,RA,RB
Pseudo-code:
Pseudo-code: