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add quick test_pysvp64dis.py of LD/ST data-dependent fail-first
[openpower-isa.git]
/
src
/
openpower
/
consts.py
diff --git
a/src/openpower/consts.py
b/src/openpower/consts.py
index f5da27b4d70cecd47631b3335edd70579c64042b..0bdfb3332e0a8acb8528056d0eaa2ede099ba523 100644
(file)
--- a/
src/openpower/consts.py
+++ b/
src/openpower/consts.py
@@
-241,10
+241,12
@@
class SVP64MODEb(_Const):
# mode bits
MOD2_MSB = 0
MOD2_LSB = 1
# mode bits
MOD2_MSB = 0
MOD2_LSB = 1
- LDST_SHIFT = 2 # set =1 for shift mode
+ MOD3 = 3
+ SEA = 2
# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
+ ZZ = 3 # for both sz/dz, on all but CR-ops, which, whoops, is RM bit 6.
# for branch-conditional
BC_SNZ = 3 # for branch-conditional mode
BC_VLI = 2 # for VL include/exclude on VLSET mode
# for branch-conditional
BC_SNZ = 3 # for branch-conditional mode
BC_VLI = 2 # for VL include/exclude on VLSET mode
@@
-252,8
+254,6
@@
class SVP64MODEb(_Const):
BC_CTRTEST = 0 # CTR-test mode
# reduce mode
REDUCE = 2 # 0=normal predication 1=reduce mode
BC_CTRTEST = 0 # CTR-test mode
# reduce mode
REDUCE = 2 # 0=normal predication 1=reduce mode
- PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
- SVM = 3 # subvector reduce mode 0=independent 1=horizontal
CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
RG = 4 # Reverse-gear on reduce
# saturation mode
CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
RG = 4 # Reverse-gear on reduce
# saturation mode
@@
-262,11
+262,15
@@
class SVP64MODEb(_Const):
INV = 2 # invert CR sense 0=set 1=unset
CR_MSB = 3 # CR bit to update (with Rc=1)
CR_LSB = 4
INV = 2 # invert CR sense 0=set 1=unset
CR_MSB = 3 # CR bit to update (with Rc=1)
CR_LSB = 4
+ VLI = 3
RC1 = 4 # update CR as if Rc=1 (when Rc=0)
# LD immediate els (element-stride) locations, depending on mode
ELS_NORMAL = 4
ELS_FFIRST_PRED = 3
ELS_SAT = 4
RC1 = 4 # update CR as if Rc=1 (when Rc=0)
# LD immediate els (element-stride) locations, depending on mode
ELS_NORMAL = 4
ELS_FFIRST_PRED = 3
ELS_SAT = 4
+ LDI_POST = 2 # LD-Immediate Post/FF Mode
+ LDI_PI = 3 # LD-Immediate Post-Increment
+ LDI_FF = 4 # LD-Immediate Fault-First
# BO bits
BO_MSB = 2
BO_LSB = 4
# BO bits
BO_MSB = 2
BO_LSB = 4
@@
-339,5
+343,6
@@
class XERRegsEnum:
OV=2 # OV and OV32
N_REGS = 3 # maximum number of regs
OV=2 # OV and OV32
N_REGS = 3 # maximum number of regs
+
if __name__ == '__main__':
print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)
if __name__ == '__main__':
print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)