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test/runner: allow disabling VCD using SIM_NO_VCD=1 env var
[openpower-isa.git]
/
src
/
openpower
/
consts.py
diff --git
a/src/openpower/consts.py
b/src/openpower/consts.py
index 65f2bc08d7b9e5d70ba67d740aa4e90f0bb55b60..2197f218ca86f3d3be5a18b7a8cecaed9d0efccd 100644
(file)
--- a/
src/openpower/consts.py
+++ b/
src/openpower/consts.py
@@
-1,4
+1,4
@@
-import enum
as _enum
+import enum
# Can't think of a better place to put these functions.
# Can't think of a better place to put these functions.
@@
-76,18
+76,18
@@
def field(r, msb0_start, msb0_end=None, field_width=64):
# this module, aside from creating various field constants,
# helps out by creating alternative (identical) classes with
# a "b" name to indicate "MSB0 big-endian".
# this module, aside from creating various field constants,
# helps out by creating alternative (identical) classes with
# a "b" name to indicate "MSB0 big-endian".
-class _Const(
_
enum.IntEnum):
+class _Const(enum.IntEnum):
pass
pass
-class _ConstLEMeta(
_
enum.EnumMeta):
+class _ConstLEMeta(enum.EnumMeta):
def __call__(metacls, *args, **kwargs):
if len(args) > 1:
names = args[1]
else:
names = kwargs.pop("names")
def __call__(metacls, *args, **kwargs):
if len(args) > 1:
names = args[1]
else:
names = kwargs.pop("names")
- if isinstance(names, type) and issubclass(names,
_
enum.Enum):
+ if isinstance(names, type) and issubclass(names, enum.Enum):
names = dict(names.__members__)
if isinstance(names, dict):
names = tuple(names.items())
names = dict(names.__members__)
if isinstance(names, dict):
names = tuple(names.items())
@@
-132,6
+132,9
@@
class MSRb(_Const):
# use this inside the HDL (where everything is little-endian)
MSR = _ConstLE("MSR", names=MSRb, msb=63)
# use this inside the HDL (where everything is little-endian)
MSR = _ConstLE("MSR", names=MSRb, msb=63)
+# default MSR value for unit tests, since 0 isn't a good default
+DEFAULT_MSR = sum(1 << i for i in (
+ MSR.SF, MSR.HV, MSR.FP, MSR.FE0, MSR.FE1, MSR.RI, MSR.LE))
# Listed in V3.0B Book III 7.5.9 "Program Interrupt"
# Listed in V3.0B Book III 7.5.9 "Program Interrupt"
@@
-242,12
+245,11
@@
class SVP64MODEb(_Const):
MOD2_MSB = 0
MOD2_LSB = 1
MOD3 = 3
MOD2_MSB = 0
MOD2_LSB = 1
MOD3 = 3
- # pack detection (TODO, CR-ops needs one of these too)
- LDST_PACK = 2 # set =1 for LD/ST-immediate Pack mode
- ARITH_PACK = 4 # set =1 for Arithmetic Pack mode
+ SEA = 2
# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
# when predicate not set: 0=ignore/skip 1=zero
DZ = 3 # for destination
SZ = 4 # for source
+ ZZ = 3 # for both sz/dz, on all but CR-ops, which, whoops, is RM bit 6.
# for branch-conditional
BC_SNZ = 3 # for branch-conditional mode
BC_VLI = 2 # for VL include/exclude on VLSET mode
# for branch-conditional
BC_SNZ = 3 # for branch-conditional mode
BC_VLI = 2 # for VL include/exclude on VLSET mode
@@
-255,20
+257,26
@@
class SVP64MODEb(_Const):
BC_CTRTEST = 0 # CTR-test mode
# reduce mode
REDUCE = 2 # 0=normal predication 1=reduce mode
BC_CTRTEST = 0 # CTR-test mode
# reduce mode
REDUCE = 2 # 0=normal predication 1=reduce mode
- SVM = 3 # subvector reduce mode 0=independent 1=horizontal
CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
RG = 4 # Reverse-gear on reduce
CRM = 4 # CR mode on reduce (Rc=1) 0=some 1=all
RG = 4 # Reverse-gear on reduce
+ CROP_RG = 3 # Reverse-gear on reduce CR-ops
# saturation mode
N = 2 # saturation signed mode 0=signed 1=unsigned
# ffirst and predicate result modes
INV = 2 # invert CR sense 0=set 1=unset
CR_MSB = 3 # CR bit to update (with Rc=1)
CR_LSB = 4
# saturation mode
N = 2 # saturation signed mode 0=signed 1=unsigned
# ffirst and predicate result modes
INV = 2 # invert CR sense 0=set 1=unset
CR_MSB = 3 # CR bit to update (with Rc=1)
CR_LSB = 4
+ VLI = 0
RC1 = 4 # update CR as if Rc=1 (when Rc=0)
# LD immediate els (element-stride) locations, depending on mode
ELS_NORMAL = 4
ELS_FFIRST_PRED = 3
RC1 = 4 # update CR as if Rc=1 (when Rc=0)
# LD immediate els (element-stride) locations, depending on mode
ELS_NORMAL = 4
ELS_FFIRST_PRED = 3
- ELS_SAT = 4
+ LDI_PI = 2 # LD-Immediate Post-Increment
+ LDI_FF = 4 # LD-Immediate Fault-First
+ # LDST element-strided
+ LDST_ELS = 0 # Indexed element-strided
+ # LDST VLI for ffirst is in bit 0
+ LDST_VLI = 0
# BO bits
BO_MSB = 2
BO_LSB = 4
# BO bits
BO_MSB = 2
BO_LSB = 4
@@
-343,4
+351,7
@@
class XERRegsEnum:
if __name__ == '__main__':
if __name__ == '__main__':
- print ("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)
+ print("EXTRA2 pack", EXTRA2.PACK_en, EXTRA2.PACK_en.value)
+ for field in MSR:
+ if DEFAULT_MSR & (1 << field.value):
+ print(field)