- if self.is_svp64_mode and insn_name.startswith("sv.bc"):
- # blegh grab bits manually
- mode = yield self.dec2.rm_dec.rm_in.mode
- # convert to SelectableInt before test
- mode = SelectableInt(mode, 5)
- bc_vlset = mode[SVP64MODEb.BC_VLSET] != 0
- bc_vli = mode[SVP64MODEb.BC_VLI] != 0
- bc_snz = mode[SVP64MODEb.BC_SNZ] != 0
- bc_vsb = yield self.dec2.rm_dec.bc_vsb
- bc_lru = yield self.dec2.rm_dec.bc_lru
- bc_gate = yield self.dec2.rm_dec.bc_gate
- sz = yield self.dec2.rm_dec.pred_sz
- self.namespace['mode'] = SelectableInt(mode, 5)
- self.namespace['ALL'] = SelectableInt(bc_gate, 1)
- self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
- self.namespace['LRu'] = SelectableInt(bc_lru, 1)
- self.namespace['VLSET'] = SelectableInt(bc_vlset, 1)
- self.namespace['VLI'] = SelectableInt(bc_vli, 1)
- self.namespace['sz'] = SelectableInt(sz, 1)
- self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
-
- def handle_carry_(self, inputs, output, ca, ca32):
+ if not self.is_svp64_mode or not insn_name.startswith("sv.bc"):
+ return
+
+ # blegh grab bits manually
+ mode = yield self.dec2.rm_dec.rm_in.mode
+ # convert to SelectableInt before test
+ mode = SelectableInt(mode, 5)
+ bc_vlset = mode[SVP64MODEb.BC_VLSET] != 0
+ bc_vli = mode[SVP64MODEb.BC_VLI] != 0
+ bc_snz = mode[SVP64MODEb.BC_SNZ] != 0
+ bc_vsb = yield self.dec2.rm_dec.bc_vsb
+ bc_ctrtest = yield self.dec2.rm_dec.bc_ctrtest
+ bc_lru = yield self.dec2.rm_dec.bc_lru
+ bc_gate = yield self.dec2.rm_dec.bc_gate
+ sz = yield self.dec2.rm_dec.pred_sz
+ self.namespace['mode'] = SelectableInt(mode, 5)
+ self.namespace['ALL'] = SelectableInt(bc_gate, 1)
+ self.namespace['VSb'] = SelectableInt(bc_vsb, 1)
+ self.namespace['LRu'] = SelectableInt(bc_lru, 1)
+ self.namespace['CTRtest'] = SelectableInt(bc_ctrtest, 1)
+ self.namespace['VLSET'] = SelectableInt(bc_vlset, 1)
+ self.namespace['VLI'] = SelectableInt(bc_vli, 1)
+ self.namespace['sz'] = SelectableInt(sz, 1)
+ self.namespace['SNZ'] = SelectableInt(bc_snz, 1)
+
+ def get_kludged_op_add_ca_ov(self, inputs, inp_ca_ov):
+ """ this was not at all necessary to do. this function massively
+ duplicates - in a laborious and complex fashion - the contents of
+ the CSV files that were extracted two years ago from microwatt's
+ source code. A-inversion is the "inv A" column, output inversion
+ is the "inv out" column, carry-in equal to 0 or 1 or CA is the
+ "cry in" column
+
+ all of that information is available in
+ self.instrs[ins_name].op_fields
+ where info is usually assigned to self.instrs[ins_name]
+
+ https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=openpower/isatables/minor_31.csv;hb=HEAD
+
+ the immediate constants are *also* decoded correctly and placed
+ usually by DecodeIn2Imm into operand2, as part of power_decoder2.py
+ """
+ def ca(a, b, ca_in, width):
+ mask = (1 << width) - 1
+ y = (a & mask) + (b & mask) + ca_in
+ return y >> width
+
+ asmcode = yield self.dec2.dec.op.asmcode
+ insn = insns.get(asmcode)
+ SI = yield self.dec2.dec.SI
+ SI &= 0xFFFF
+ CA, OV = inp_ca_ov
+ inputs = [i.value for i in inputs]
+ if SI & 0x8000:
+ SI -= 0x10000
+ if insn in ("add", "addo", "addc", "addco"):
+ a = inputs[0]
+ b = inputs[1]
+ ca_in = 0
+ elif insn == "addic" or insn == "addic.":
+ a = inputs[0]
+ b = SI
+ ca_in = 0
+ elif insn in ("subf", "subfo", "subfc", "subfco"):
+ a = ~inputs[0]
+ b = inputs[1]
+ ca_in = 1
+ elif insn == "subfic":
+ a = ~inputs[0]
+ b = SI
+ ca_in = 1
+ elif insn == "adde" or insn == "addeo":
+ a = inputs[0]
+ b = inputs[1]
+ ca_in = CA
+ elif insn == "subfe" or insn == "subfeo":
+ a = ~inputs[0]
+ b = inputs[1]
+ ca_in = CA
+ elif insn == "addme" or insn == "addmeo":
+ a = inputs[0]
+ b = ~0
+ ca_in = CA
+ elif insn == "addze" or insn == "addzeo":
+ a = inputs[0]
+ b = 0
+ ca_in = CA
+ elif insn == "subfme" or insn == "subfmeo":
+ a = ~inputs[0]
+ b = ~0
+ ca_in = CA
+ elif insn == "subfze" or insn == "subfzeo":
+ a = ~inputs[0]
+ b = 0
+ ca_in = CA
+ elif insn == "addex":
+ # CA[32] aren't actually written, just generate so we have
+ # something to return
+ ca64 = ov64 = ca(inputs[0], inputs[1], OV, 64)
+ ca32 = ov32 = ca(inputs[0], inputs[1], OV, 32)
+ return ca64, ca32, ov64, ov32
+ elif insn == "neg" or insn == "nego":
+ a = ~inputs[0]
+ b = 0
+ ca_in = 1
+ else:
+ raise NotImplementedError(
+ "op_add kludge unimplemented instruction: ", asmcode, insn)
+
+ ca64 = ca(a, b, ca_in, 64)
+ ca32 = ca(a, b, ca_in, 32)
+ ov64 = ca64 != ca(a, b, ca_in, 63)
+ ov32 = ca32 != ca(a, b, ca_in, 31)
+ return ca64, ca32, ov64, ov32
+
+ def handle_carry_(self, inputs, output, ca, ca32, inp_ca_ov):
+ if ca is not None and ca32 is not None:
+ return
+ op = yield self.dec2.e.do.insn_type
+ if op == MicrOp.OP_ADD.value and ca is None and ca32 is None:
+ retval = yield from self.get_kludged_op_add_ca_ov(
+ inputs, inp_ca_ov)
+ ca, ca32, ov, ov32 = retval
+ asmcode = yield self.dec2.dec.op.asmcode
+ if insns.get(asmcode) == 'addex':
+ # TODO: if 32-bit mode, set ov to ov32
+ self.spr['XER'][XER_bits['OV']] = ov
+ self.spr['XER'][XER_bits['OV32']] = ov32
+ log(f"write OV/OV32 OV={ov} OV32={ov32}",
+ kind=LogType.InstrInOuts)
+ else:
+ # TODO: if 32-bit mode, set ca to ca32
+ self.spr['XER'][XER_bits['CA']] = ca
+ self.spr['XER'][XER_bits['CA32']] = ca32
+ log(f"write CA/CA32 CA={ca} CA32={ca32}",
+ kind=LogType.InstrInOuts)
+ return
projects / openpower-isa.git / blobdiff