+ WARNING: this function uses information that was created EARLIER
+ due to it being in the middle of a yield, but this function is
+ *NOT* called from yield (it's called from compiled pseudocode).
+ """
+ self.allow_next_step_inc = submode.value + 1
+ log("SVSTATE_NEXT mode", mode, submode, self.allow_next_step_inc)
+ self.svstate_next_mode = mode
+ if self.svstate_next_mode > 0 and self.svstate_next_mode < 5:
+ shape_idx = self.svstate_next_mode.value-1
+ return SelectableInt(self.remap_idxs[shape_idx], 7)
+ if self.svstate_next_mode == 5:
+ self.svstate_next_mode = 0
+ return SelectableInt(self.svstate.srcstep, 7)
+ if self.svstate_next_mode == 6:
+ self.svstate_next_mode = 0
+ return SelectableInt(self.svstate.dststep, 7)
+ return SelectableInt(0, 7)
+
+ def svstate_pre_inc(self):
+ """check if srcstep/dststep need to skip over masked-out predicate bits
+ note that this is not supposed to do anything to substep,
+ it is purely for skipping masked-out bits
+ """
+ # get SVSTATE VL (oh and print out some debug stuff)
+ vl = self.svstate.vl
+ subvl = yield self.dec2.rm_dec.rm_in.subvl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ ssubstep = self.svstate.ssubstep
+ dsubstep = self.svstate.dsubstep
+ sv_a_nz = yield self.dec2.sv_a_nz
+ fft_mode = yield self.dec2.use_svp64_fft
+ in1 = yield self.dec2.e.read_reg1.data
+ log("SVP64: VL, subvl, srcstep, dststep, ssubstep, dsybstep, sv_a_nz, "
+ "in1 fft, svp64",
+ vl, subvl, srcstep, dststep, ssubstep, dsubstep,
+ sv_a_nz, in1, fft_mode,
+ self.is_svp64_mode)
+
+ # get predicate mask (all 64 bits)
+ srcmask = dstmask = 0xffff_ffff_ffff_ffff
+
+ pmode = yield self.dec2.rm_dec.predmode
+ pack = yield self.dec2.rm_dec.pack
+ unpack = yield self.dec2.rm_dec.unpack
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ srcpred = yield self.dec2.rm_dec.srcpred
+ dstpred = yield self.dec2.rm_dec.dstpred
+ pred_src_zero = yield self.dec2.rm_dec.pred_sz
+ pred_dst_zero = yield self.dec2.rm_dec.pred_dz
+ if pmode == SVP64PredMode.INT.value:
+ srcmask = dstmask = get_predint(self.gpr, dstpred)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predint(self.gpr, srcpred)
+ elif pmode == SVP64PredMode.CR.value:
+ srcmask = dstmask = get_predcr(self.crl, dstpred, vl)
+ if sv_ptype == SVPtype.P2.value:
+ srcmask = get_predcr(self.crl, srcpred, vl)
+ # work out if the ssubsteps are completed
+ ssubstart = ssubstep == 0
+ dsubstart = dsubstep == 0
+ log(" pmode", pmode)
+ log(" pack/unpack", pack, unpack)
+ log(" reverse", reverse_gear)
+ log(" ptype", sv_ptype)
+ log(" srcpred", bin(srcpred))
+ log(" dstpred", bin(dstpred))
+ log(" srcmask", bin(srcmask))
+ log(" dstmask", bin(dstmask))
+ log(" pred_sz", bin(pred_src_zero))
+ log(" pred_dz", bin(pred_dst_zero))
+ log(" ssubstart", ssubstart)
+ log(" dsubstart", dsubstart)
+
+ # okaaay, so here we simply advance srcstep (TODO dststep)
+ # this can ONLY be done at the beginning of the "for" loop
+ # (this is all actually a FSM so it's hell to keep track sigh)
+ if ssubstart:
+ # until the predicate mask has a "1" bit... or we run out of VL
+ # let srcstep==VL be the indicator to move to next instruction
+ if not pred_src_zero:
+ while (((1 << srcstep) & srcmask) == 0) and (srcstep != vl):
+ log(" sskip", bin(1 << srcstep))
+ srcstep += 1
+ if dsubstart:
+ # same for dststep
+ if not pred_dst_zero:
+ while (((1 << dststep) & dstmask) == 0) and (dststep != vl):
+ log(" dskip", bin(1 << dststep))
+ dststep += 1
+
+ # now work out if the relevant mask bits require zeroing
+ if pred_dst_zero:
+ pred_dst_zero = ((1 << dststep) & dstmask) == 0
+ if pred_src_zero:
+ pred_src_zero = ((1 << srcstep) & srcmask) == 0
+
+ # store new srcstep / dststep
+ self.new_srcstep, self.new_dststep = (srcstep, dststep)
+ self.new_ssubstep, self.new_dsubstep = (ssubstep, dsubstep)
+ self.pred_dst_zero, self.pred_src_zero = (pred_dst_zero, pred_src_zero)
+ log(" new srcstep", srcstep)
+ log(" new dststep", dststep)
+ log(" new ssubstep", ssubstep)
+ log(" new dsubstep", dsubstep)
+
+ def get_src_dststeps(self):
+ """gets srcstep, dststep, and ssubstep, dsubstep
+ """
+ return (self.new_srcstep, self.new_dststep,
+ self.new_ssubstep, self.new_dsubstep)
+
+ def update_new_svstate_steps(self):
+ # note, do not get the bit-reversed srcstep here!
+ srcstep, dststep = self.new_srcstep, self.new_dststep
+ ssubstep, dsubstep = self.new_ssubstep, self.new_dsubstep
+
+ # update SVSTATE with new srcstep
+ self.svstate.srcstep = srcstep
+ self.svstate.dststep = dststep
+ self.svstate.ssubstep = ssubstep
+ self.svstate.dsubstep = dsubstep
+ self.namespace['SVSTATE'] = self.svstate
+ yield self.dec2.state.svstate.eq(self.svstate.value)
+ yield Settle() # let decoder update
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ ssubstep = self.svstate.ssubstep
+ dsubstep = self.svstate.dsubstep
+ vl = self.svstate.vl
+ subvl = yield self.dec2.rm_dec.rm_in.subvl
+ log(" srcstep", srcstep)
+ log(" dststep", dststep)
+ log(" ssubstep", ssubstep)
+ log(" dsubstep", dsubstep)
+ log(" vl", vl)
+ log(" subvl", subvl)
+
+ # check if end reached (we let srcstep overrun, above)
+ # nothing needs doing (TODO zeroing): just do next instruction
+ return srcstep == vl or dststep == vl
+
+ def svstate_post_inc(self, insn_name, vf=0):
+ # check if SV "Vertical First" mode is enabled
+ vfirst = self.svstate.vfirst
+ log(" SV Vertical First", vf, vfirst)
+ if not vf and vfirst == 1:
+ self.update_nia()
+ return True
+
+ # check if it is the SVSTATE.src/dest step that needs incrementing
+ # this is our Sub-Program-Counter loop from 0 to VL-1
+ # XXX twin predication TODO
+ vl = self.svstate.vl
+ subvl = yield self.dec2.rm_dec.rm_in.subvl
+ mvl = self.svstate.maxvl
+ srcstep = self.svstate.srcstep
+ dststep = self.svstate.dststep
+ ssubstep = self.svstate.ssubstep
+ dsubstep = self.svstate.dsubstep
+ rm_mode = yield self.dec2.rm_dec.mode
+ reverse_gear = yield self.dec2.rm_dec.reverse_gear
+ sv_ptype = yield self.dec2.dec.op.SV_Ptype
+ out_vec = not (yield self.dec2.no_out_vec)
+ in_vec = not (yield self.dec2.no_in_vec)
+ log(" svstate.vl", vl)
+ log(" svstate.mvl", mvl)
+ log(" rm.subvl", subvl)
+ log(" svstate.srcstep", srcstep)
+ log(" svstate.dststep", dststep)
+ log(" svstate.ssubstep", ssubstep)
+ log(" svstate.dsubstep", dsubstep)
+ log(" mode", rm_mode)
+ log(" reverse", reverse_gear)
+ log(" out_vec", out_vec)
+ log(" in_vec", in_vec)
+ log(" sv_ptype", sv_ptype, sv_ptype == SVPtype.P2.value)
+ # check if srcstep needs incrementing by one, stop PC advancing
+ # svp64 loop can end early if the dest is scalar for single-pred
+ # but for 2-pred both src/dest have to be checked.
+ # XXX this might not be true! it may just be LD/ST
+ if sv_ptype == SVPtype.P2.value:
+ svp64_is_vector = (out_vec or in_vec)
+ else:
+ svp64_is_vector = out_vec
+ # check if this was an sv.bc* and if so did it succeed
+ if self.is_svp64_mode and insn_name.startswith("sv.bc"):
+ end_loop = self.namespace['end_loop']
+ log("branch %s end_loop" % insn_name, end_loop)
+ if end_loop.value:
+ self.svp64_reset_loop()
+ self.update_pc_next()
+ return False
+ # loops end at the first "hit" (source or dest)
+ loopend = ((srcstep == vl-1 and ssubstep == subvl) or
+ (dststep == vl-1 and dsubstep == subvl))
+ if not svp64_is_vector or loopend:
+ # reset loop to zero and update NIA
+ self.svp64_reset_loop()
+ self.update_nia()
+
+ return True
+
+ # still looping, advance and update NIA
+ yield from self.advance_svstate_steps()
+ self.namespace['SVSTATE'] = self.svstate
+ # not an SVP64 branch, so fix PC (NIA==CIA) for next loop
+ # (by default, NIA is CIA+4 if v3.0B or CIA+8 if SVP64)
+ # this way we keep repeating the same instruction (with new steps)
+ self.pc.NIA.value = self.pc.CIA.value
+ self.namespace['NIA'] = self.pc.NIA
+ log("end of sub-pc call", self.namespace['CIA'], self.namespace['NIA'])
+ return False # DO NOT allow PC update whilst Sub-PC loop running
+
+ def advance_svstate_steps(self, end_src=False, end_dst=False):
+ """ advance sub/steps. note that Pack/Unpack *INVERTS* the order.
+ TODO when Pack/Unpack is set, substep becomes the *outer* loop
+ """
+ subvl = yield self.dec2.rm_dec.rm_in.subvl
+ # first source step
+ ssubstep = self.svstate.ssubstep
+ end_sub = ssubstep == subvl
+ if end_sub:
+ if not end_src:
+ self.svstate.srcstep += SelectableInt(1, 7)
+ self.svstate.ssubstep = SelectableInt(0, 2) # reset
+ else:
+ self.svstate.ssubstep += SelectableInt(1, 2) # advance ssubstep
+ # now dest step
+ dsubstep = self.svstate.dsubstep
+ end_sub = dsubstep == subvl
+ if end_sub:
+ if not end_dst:
+ self.svstate.dststep += SelectableInt(1, 7)
+ self.svstate.dsubstep = SelectableInt(0, 2) # reset
+ else:
+ self.svstate.dsubstep += SelectableInt(1, 2) # advance ssubstep