- comb += rm_dec.fn_in.eq(fn) # decode needs to know if LD/ST type
- comb += rm_dec.ptype_in.eq(op.SV_Ptype) # Single/Twin predicated
- comb += rm_dec.rc_in.eq(rc_out) # Rc=1
- comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
- bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
- comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
- comb += rm_dec.ldst_ra_vec.eq(self.in1_isvec) # RA is vector
+ # detect major opcode for LDs: include 58 here. from CSV files.
+ # BLECH! TODO: these should be done using "mini decoders",
+ # using row and column subsets
+ is_major_ld = Signal()
+ # bits... errr... MSB0 0..5 which is 26:32 python
+ major = Signal(6)
+ comb += major.eq(self.dec.opcode_in[26:32])
+ comb += is_major_ld.eq((major == 34) | (major == 35) |
+ (major == 50) | (major == 51) |
+ (major == 48) | (major == 49) |
+ (major == 42) | (major == 43) |
+ (major == 40) | (major == 41) |
+ (major == 32) | (major == 33) |
+ (major == 58))
+ with m.If(self.is_svp64_mode & is_major_ld):
+ # straight-up: "it's a LD". this gives enough info
+ # for SVP64 RM Mode decoding to detect LD/ST, and
+ # consequently detect the SHIFT mode. sigh
+ comb += rm_dec.fn_in.eq(Function.LDST)
+ with m.Else():
+ comb += rm_dec.fn_in.eq(fn) # decode needs to know Fn type
+ comb += rm_dec.ptype_in.eq(sv_ptype) # Single/Twin predicated
+ comb += rm_dec.rc_in.eq(rc_out) # Rc=1
+ comb += rm_dec.rm_in.eq(self.sv_rm) # SVP64 RM mode
+ if self.needs_field("imm_data", "in2_sel"):
+ bzero = dec_bi.imm_out.ok & ~dec_bi.imm_out.data.bool()
+ comb += rm_dec.ldst_imz_in.eq(bzero) # B immediate is zero
+
+ # main PowerDecoder2 determines if different SVP64 modes enabled
+ if not self.final:
+ # if shift mode requested
+ shiftmode = rm_dec.ldstmode == SVP64LDSTmode.SHIFT
+ comb += self.use_svp64_ldst_dec.eq(shiftmode)
+ # detect if SVP64 FFT mode enabled (really bad hack),
+ # exclude fcfids and others
+ # XXX this is a REALLY bad hack, REALLY has to be done better.
+ # likely with a sub-decoder.
+ xo5 = Signal(1) # 1 bit from Minor 59 XO field == 0b0XXXX
+ comb += xo5.eq(self.dec.opcode_in[5])
+ xo = Signal(5) # 5 bits from Minor 59 fcfids == 0b01110
+ comb += xo.eq(self.dec.opcode_in[1:6])
+ comb += self.use_svp64_fft.eq((major == 59) & (xo5 == 0b0) &
+ (xo != 0b01110))