sv.bc test jumping to wrong location (offset 0xc not 0x8)

[openpower-isa.git] / src / openpower / decoder / power_enums.py

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 4b94527392b8f2d24dceda93c84479eb1a5bb148..eee86b949e7d18675b798caf6289f2152761223e 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -81,6 +81,7 @@ class Function(Enum):
     MMU = 1 << 11
     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
     VL = 1 << 13  # setvl
     MMU = 1 << 11
     SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
     VL = 1 << 13  # setvl

+    FPU = 1 << 14  # FPU

 
 
 @unique
 
 
 @unique


@@ -115,6 +116,10 @@ class Form(Enum):
     Z22 = 27
     Z23 = 28
     SVL = 29  # Simple-V for setvl instruction
     Z22 = 27
     Z23 = 28
     SVL = 29  # Simple-V for setvl instruction

+    SVD = 30  # Simple-V for LD/ST bit-reverse, variant of D-Form
+    SVDS = 31  # Simple-V for LD/ST bit-reverse, variant of DS-Form
+    SVM = 32  # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY
+    SVRM = 33  # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY

 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 


@@ -181,6 +186,35 @@ class SVP64RMMode(Enum):
     FFIRST = 2
     SATURATE = 3
     PREDRES = 4
     FFIRST = 2
     SATURATE = 3
     PREDRES = 4

+    BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+    NONE = 0
+    MASKZERO = 1
+    MASKONE = 2
+
+@unique
+class SVP64BCVLSETMode(Enum):
+    NONE = 0
+    VL_INCL = 1
+    VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4.  ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+    ANY = 0
+    ALL = 1
+
+
+@unique
+class SVP64BCStep(Enum):
+    NONE = 0
+    STEP = 1
+    STEP_RC = 2

 
 
 @unique
 
 
 @unique


@@ -205,6 +239,14 @@ class SVP64sat(Enum):
     SIGNED = 1
     UNSIGNED = 2
 
     SIGNED = 1
     UNSIGNED = 2
 

+@unique
+class SVP64LDSTmode(Enum):
+    NONE = 0
+    INDEXED = 1
+    ELSTRIDE = 2
+    UNITSTRIDE = 3
+    SHIFT = 4
+

 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else


@@ -212,10 +254,13 @@ _insns = [
     "NONE", "add", "addc", "addco", "adde", "addeo",
     "addi", "addic", "addic.", "addis",
     "addme", "addmeo", "addo", "addze", "addzeo",
     "NONE", "add", "addc", "addco", "adde", "addeo",
     "addi", "addic", "addic.", "addis",
     "addme", "addmeo", "addo", "addze", "addzeo",

+    "addg6s",

     "and", "andc", "andi.", "andis.",
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",
     "and", "andc", "andi.", "andis.",
     "attn",
     "b", "bc", "bcctr", "bclr", "bctar",
     "bpermd",

+    "cbcdtd",
+    "cdtbcd",

     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
     "crand", "crandc", "creqv",
     "cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
     "cntlzd", "cntlzw", "cnttzd", "cnttzw",
     "crand", "crandc", "creqv",


@@ -227,15 +272,31 @@ _insns = [
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
     "eqv",
     "extsb", "extsh", "extsw", "extswsli",
     "divweu", "divweuo", "divwo", "divwu", "divwuo",
     "eqv",
     "extsb", "extsh", "extsw", "extswsli",

+    "fadd", "fadds", "fsub", "fsubs",                   # FP add / sub
+    "fcfids", "fcfidus", "fsqrts", "fres", "frsqrtes",  # FP stuff
+    "fdmadds",                                          # DCT FP 3-arg
+    "fmsubs", "fmadds", "fnmsubs", "fnmadds",           # FP 3-arg
+    "ffadds", "ffsubs", "ffmuls", "ffdivs",             # FFT FP 2-arg
+    "ffmsubs", "ffmadds", "ffnmsubs", "ffnmadds",       # FFT FP 3-arg
+    "fmul", "fmuls", "fdiv", "fdivs",                   # FP mul / div
+    "fmr", "fabs", "fnabs", "fneg", "fcpsgn",           # FP move/abs/neg
+    "fsins", "fcoss",                                   # FP SIN/COS

     "hrfid", "icbi", "icbt", "isel", "isync",
     "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
     "hrfid", "icbi", "icbt", "isel", "isync",
     "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
     "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double

+    #"lbzbr", "lbzubr",  # load byte SVP64 bit-reversed
+    #"ldbr", "ldubr",    # load double SVP64 bit-reversed

     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
     "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
     "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
     "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
     "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half

+    #"lhabr", "lhaubr",  # load half SVP64 bit-reversed
+    #"lhzbr", "lhzubr",  # more load half SVP64 bit-reversed

     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
     "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
     "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word

+    #"lwabr",           # load word SVP64 bit-reversed
+    #"lwzbr", "lwzubr", # more load word SVP64 bit-reversed
+    "maddhd", "maddhdu", "maddld",                      # INT multiply-and-add

     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
     "modsd", "modsw", "modud", "moduw",
     "mcrf", "mcrxr", "mcrxrx", "mfcr/mfocrf",           # CR mvs
     "mfmsr", "mfspr",
     "modsd", "modsw", "modud", "moduw",


@@ -252,11 +313,16 @@ _insns = [
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "rlwimi", "rlwinm",    "rlwnm",
     "setb",
     "setvl",  # https://libre-soc.org/openpower/sv/setvl

+    "svremap",  # https://libre-soc.org/openpower/sv/remap - TEMPORARY
+    "svshape",  # https://libre-soc.org/openpower/sv/remap
+    "svstep",  # https://libre-soc.org/openpower/sv/setvl

     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
     "sim_cfg",
     "slbia", "sld", "slw", "srad", "sradi",
     "sraw", "srawi", "srd", "srw",
     "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",

+    "stfs", "stfsx", "stfsu", "stfux",                  # FP store single
+    "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store double

     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",
     "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
     "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
     "subf", "subfc", "subfco", "subfe", "subfeo", "subfic",


@@ -275,6 +341,9 @@ for i, insn in enumerate(_insns):
     insns[i] = insn
     asmidx[insn] = i
 
     insns[i] = insn
     asmidx[insn] = i
 

+# must be long enough to cover all instructions
+asmlen = len(_insns).bit_length()
+

 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
 
 


@@ -354,6 +423,15 @@ class MicrOp(Enum):
     OP_MTMSR = 74
     OP_TLBIE = 75
     OP_SETVL = 76
     OP_MTMSR = 74
     OP_TLBIE = 75
     OP_SETVL = 76

+    OP_FPOP = 77  # temporary: replace with actual ops
+    OP_FPOP_I = 78 # temporary: replace with actual ops
+    OP_FP_MADD = 79
+    OP_SVREMAP = 80
+    OP_SVSHAPE = 81
+    OP_SVSTEP = 82
+    OP_ADDG6S = 83
+    OP_CDTBCD = 84
+    OP_CBCDTD = 85

 
 
 @unique
 
 
 @unique


@@ -384,6 +462,8 @@ class In2Sel(Enum):
     SPR = 12
     RS = 13  # for shiftrot (M-Form)
     FRB = 14
     SPR = 12
     RS = 13  # for shiftrot (M-Form)
     FRB = 14

+    CONST_SVD = 15 # for SVD-Form
+    CONST_SVDS = 16 # for SVDS-Form

 
 
 @unique
 
 
 @unique


@@ -393,6 +473,7 @@ class In3Sel(Enum):
     RB = 2  # for shiftrot (M-Form)
     FRS = 3
     FRC = 4
     RB = 2  # for shiftrot (M-Form)
     FRS = 3
     FRC = 4

+    RC = 5  # for SVP64 bit-reverse LD/ST

 
 
 @unique
 
 
 @unique


@@ -403,6 +484,7 @@ class OutSel(Enum):
     SPR = 3
     RT_OR_ZERO = 4
     FRT = 5
     SPR = 3
     RT_OR_ZERO = 4
     FRT = 5

+    FRS = 6

 
 
 @unique
 
 
 @unique


@@ -469,6 +551,7 @@ def get_spr_enum(full_file):
     this saves drastically on the size of the regfile
     """
     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',
     this saves drastically on the size of the regfile
     """
     short_list = {'PIDR', 'DAR', 'PRTBL', 'DSISR', 'SVSRR0', 'SVSTATE',

+                  'SVSTATE0', 'SVSTATE1', 'SVSTATE2', 'SVSTATE3',

                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
                   'SPRG3'
                  }
                   'SPRG0_priv', 'SPRG1_priv', 'SPRG2_priv', 'SPRG3_priv',
                   'SPRG3'
                  }