+ BRANCH = 5
+
+
+@unique
+class SVP64BCPredMode(Enum):
+ NONE = 0
+ MASKZERO = 1
+ MASKONE = 2
+
+@unique
+class SVP64BCVLSETMode(Enum):
+ NONE = 0
+ VL_INCL = 1
+ VL_EXCL = 2
+
+
+# note that these are chosen to be exactly the same as
+# SVP64 RM bit 4. ALL=1 => bit4=1
+@unique
+class SVP64BCGate(Enum):
+ ANY = 0
+ ALL = 1
+
+
+@unique
+class SVP64BCStep(Enum):
+ NONE = 0
+ STEP = 1
+ STEP_RC = 2
"NONE", "add", "addc", "addco", "adde", "addeo",
"addi", "addic", "addic.", "addis",
"addme", "addmeo", "addo", "addze", "addzeo",
"NONE", "add", "addc", "addco", "adde", "addeo",
"addi", "addic", "addic.", "addis",
"addme", "addmeo", "addo", "addze", "addzeo",
"and", "andc", "andi.", "andis.",
"attn",
"b", "bc", "bcctr", "bclr", "bctar",
"bpermd",
"and", "andc", "andi.", "andis.",
"attn",
"b", "bc", "bcctr", "bclr", "bctar",
"bpermd",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
"cntlzd", "cntlzw", "cnttzd", "cnttzw",
"crand", "crandc", "creqv",
"cmp", "cmpb", "cmpeqb", "cmpi", "cmpl", "cmpli", "cmprb",
"cntlzd", "cntlzw", "cnttzd", "cnttzw",
"crand", "crandc", "creqv",
"setvl", # https://libre-soc.org/openpower/sv/setvl
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape", # https://libre-soc.org/openpower/sv/remap
"setvl", # https://libre-soc.org/openpower/sv/setvl
"svremap", # https://libre-soc.org/openpower/sv/remap - TEMPORARY
"svshape", # https://libre-soc.org/openpower/sv/remap
"sim_cfg",
"slbia", "sld", "slw", "srad", "sradi",
"sraw", "srawi", "srd", "srw",
"sim_cfg",
"slbia", "sld", "slw", "srad", "sradi",
"sraw", "srawi", "srd", "srw",