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power_insn: slightly change table checking style
[openpower-isa.git]
/
src
/
openpower
/
decoder
/
power_regspec_map.py
diff --git
a/src/openpower/decoder/power_regspec_map.py
b/src/openpower/decoder/power_regspec_map.py
index 151cb7ee19ab912c39178f189179ee2d9c42b201..71fbb2823961976574dd9c596eac761b4278086b 100644
(file)
--- a/
src/openpower/decoder/power_regspec_map.py
+++ b/
src/openpower/decoder/power_regspec_map.py
@@
-104,18
+104,20
@@
def regspec_decode_read(m, e, regfile, name):
SVSTATE = 1<<StateRegsEnum.SVSTATE
if name in ['cia', 'nia']:
# TODO: detect read-conditions
SVSTATE = 1<<StateRegsEnum.SVSTATE
if name in ['cia', 'nia']:
# TODO: detect read-conditions
- rd = RegDecodeInfo(Const(1), PC,
3
)
+ rd = RegDecodeInfo(Const(1), PC,
5
)
if name == 'msr':
# TODO: detect read-conditions
if name == 'msr':
# TODO: detect read-conditions
- rd = RegDecodeInfo(Const(1), MSR,
3
)
+ rd = RegDecodeInfo(Const(1), MSR,
5
)
if name == 'svstate':
# TODO: detect read-conditions
if name == 'svstate':
# TODO: detect read-conditions
- rd = RegDecodeInfo(Const(1), SVSTATE, 3)
+ rd = RegDecodeInfo(Const(1), SVSTATE, 5)
+ if name == 'state1':
+ rd = RegDecodeInfo(e.read_state1.ok, 1<<e.read_state1.data, 5)
# FAST regfile
if regfile == 'FAST':
# FAST regfile
if regfile == 'FAST':
- # FAST register numbering is *
u
nary* encoded
+ # FAST register numbering is *
bi
nary* encoded
if name == 'fast1':
rd = RegDecodeInfo(e.read_fast1.ok, e.read_fast1.data, 4)
if name == 'fast2':
if name == 'fast1':
rd = RegDecodeInfo(e.read_fast1.ok, e.read_fast1.data, 4)
if name == 'fast2':
@@
-194,16
+196,18
@@
def regspec_decode_write(m, e, regfile, name):
MSR = 1<<StateRegsEnum.MSR
SVSTATE = 1<<StateRegsEnum.SVSTATE
if name in ['cia', 'nia']:
MSR = 1<<StateRegsEnum.MSR
SVSTATE = 1<<StateRegsEnum.SVSTATE
if name in ['cia', 'nia']:
- wr = RegDecodeInfo(None, PC,
3
) # hmmm
+ wr = RegDecodeInfo(None, PC,
5
) # hmmm
if name == 'msr':
if name == 'msr':
- wr = RegDecodeInfo(None, MSR,
3
) # hmmm
+ wr = RegDecodeInfo(None, MSR,
5
) # hmmm
if name == 'svstate':
if name == 'svstate':
- wr = RegDecodeInfo(None, SVSTATE, 3) # hmmm
+ wr = RegDecodeInfo(None, SVSTATE, 5) # hmmm
+ if name == 'state1':
+ wr = RegDecodeInfo(e.write_state1.ok, 1<<e.write_state1.data, 5)
# FAST regfile
if regfile == 'FAST':
# FAST regfile
if regfile == 'FAST':
- # FAST register numbering is *
u
nary* encoded
+ # FAST register numbering is *
bi
nary* encoded
if name == 'fast1':
wr = RegDecodeInfo(e.write_fast1.ok, e.write_fast1.data, 4)
if name == 'fast2':
if name == 'fast1':
wr = RegDecodeInfo(e.write_fast1.ok, e.write_fast1.data, 4)
if name == 'fast2':