- print("regs", test.regs)
- print("sprs", test.sprs)
- print("cr", test.cr)
- print("mem", test.mem)
- print("msr", test.msr)
- print("assem", program.assembly)
+
+ def format_regs(regs):
+ # type: (list[int]) -> str
+ out = []
+ for i, v in enumerate(regs):
+ values = ""
+ for sz in (32, 64):
+ for signed in ("u", "i"):
+ value = v % (1 << sz)
+ if signed == "i" and \
+ value & (1 << (sz - 1)) != 0:
+ value -= 1 << sz
+ values += f" {signed}{sz}:{value}"
+ out.append(f"r{i} = 0x{v:X} {values}")
+ return "\n".join(out)
+ log("regs:", format_regs(test.regs),
+ kind=LogKind.InstrInOuts)
+ log("sprs", test.sprs, kind=LogKind.InstrInOuts)
+ log("cr", test.cr, kind=LogKind.InstrInOuts)
+ log("mem", test.mem)
+ log("msr", test.msr, kind=LogKind.InstrInOuts)
+
+ def format_assembly(assembly):
+ # type: (str) -> str
+ pc = 0
+ out = []
+ for line in assembly.splitlines():
+ out.append(f"pc=0x{pc:04X}: {line}")
+ if not line.startswith(".set ") and \
+ line.partition('#')[0].strip() != "":
+ pc += 4
+ return "\n".join(out)
+ log("assembly:\n" + format_assembly(program.assembly),
+ kind=LogKind.InstrInOuts)