+ def compare_mem(self, s2):
+ # copy dics to preserve state mem then pad empty locs since
+ # different Power ISA objects may differ how theystore memory
+ s1mem, s2mem = self.mem.copy(), s2.mem.copy()
+ for i in set(self.mem).difference(set(s2.mem)):
+ s2mem[i] = 0
+ for i in set(s2.mem).difference(set(self.mem)):
+ s1mem[i] = 0
+ for i in s1mem:
+ self.dut.assertEqual(s1mem[i], s2mem[i],
+ "mem mismatch location %d %s" % (i, self.code))
+
+ def dump_state_tofile(self, testname=None, testfile=None):
+ """dump_state_tofile: Takes a passed in teststate object along
+ with a test name and generates a code file located at
+ /tmp/testfile/testname to set an expected state object
+ """
+ lindent = ' '*8 # indent for code
+ # create the path
+ if testname is not None:
+ path = "/tmp/expected/"
+ if testfile is not None:
+ path += testfile + '/'
+ os.makedirs(path, exist_ok=True)
+ sout = open("%s%s.py" % (path, testname), "a+")
+ else:
+ sout = sys.stdout
+
+ # pc and intregs
+ sout.write("%se = ExpectedState(pc=%d)\n" % (lindent, self.pc))
+ for i, reg in enumerate(self.intregs):
+ if(reg != 0):
+ msg = "%se.intregs[%d] = 0x%x\n"
+ sout.write( msg % (lindent, i, reg))
+ # CR fields
+ for i in range(8):
+ cri = self.crregs[i]
+ if(cri != 0):
+ msg = "%se.crregs[%d] = 0x%x\n"
+ sout.write( msg % (lindent, i, cri))
+ # XER
+ if(self.so != 0):
+ sout.write("%se.so = 0x%x\n" % (lindent, self.so))
+ if(self.ov != 0):
+ sout.write("%se.ov = 0x%x\n" % (lindent, self.ov))
+ if(self.ca != 0):
+ sout.write("%se.ca = 0x%x\n" % (lindent, self.ca))
+
+ if sout != sys.stdout:
+ sout.close()
+