+ # fpscr
+ if self.fpscr is not None and s2.fpscr is not None:
+ if self.fpscr != s2.fpscr:
+ # use FPSCRState.fsi since that's much easier to read than a
+ # decimal integer and since unittest has fancy dict diffs.
+
+ # use auto_update_summary_bits=False since HDL might
+ # mis-compute those summary bits and we want to show the
+ # actual bits, not the corrected bits
+ fpscr1 = FPSCRState(self.fpscr, auto_update_summary_bits=False)
+ fpscr2 = FPSCRState(s2.fpscr, auto_update_summary_bits=False)
+ # FieldSelectableInt.__repr__ is too long
+ fpscr1 = {k: hex(int(v)) for k, v in fpscr1.fsi.items()}
+ fpscr2 = {k: hex(int(v)) for k, v in fpscr2.fsi.items()}
+ old_max_diff = self.dut.maxDiff
+ self.dut.maxDiff = None # show full diff
+ try:
+ self.dut.assertEqual(
+ fpscr1, fpscr2, "fpscr mismatch (%s != %s) %s\n" %
+ (self.state_type, s2.state_type, repr(self.code)))
+ finally:
+ self.dut.maxDiff = old_max_diff
+
+ for spr in self.sprs:
+ spr1 = self.sprs[spr]
+ spr2 = s2.sprs[spr]
+
+ if spr1 == spr2:
+ continue
+
+ if spr1 is not None and spr2 is not None:
+ # if not explicitly ignored
+
+ self.dut.fail(
+ f"{spr1:#x} != {spr2:#x}: {spr} mismatch "
+ f"({self.state_type} != {s2.state_type}) {self.code!r}\n")
+
+ if self.msr is not None and s2.msr is not None:
+ self.dut.assertEqual(
+ hex(self.msr), hex(s2.msr), "msr mismatch (%s != %s) %s" %
+ (self.state_type, s2.state_type, repr(self.code)))
+