+ bank, check=True)
+
+# Shadow reg container class
+class GPIOConfigReg():
+ def __init__(self, shift_dict):
+ self.shift_dict = shift_dict
+ self.oe=0
+ self.ie=0
+ self.puen=0
+ self.pden=0
+ self.io=0
+ self.bank=0
+ self.packed=0
+
+ def set(self, oe=0, ie=0, puen=0, pden=0, io=0, bank=0):
+ self.oe=oe
+ self.ie=ie
+ self.puen=puen
+ self.pden=pden
+ self.io=io
+ self.bank=bank
+ self.pack() # Produce packed byte for sending
+
+ def set_out(self, outval):
+ self.io=outval
+ self.pack() # Produce packed byte for sending
+
+ # Take config parameters of specified GPIOs, and combine them to produce
+ # bytes for sending via WB bus
+ def pack(self):
+ self.packed = ((self.oe << self.shift_dict['oe'])
+ | (self.ie << self.shift_dict['ie'])
+ | (self.puen << self.shift_dict['puen'])
+ | (self.pden << self.shift_dict['pden'])
+ | (self.io << self.shift_dict['io'])
+ | (self.bank << self.shift_dict['bank']))
+
+ #print("GPIO Packed CSR: {0:x}".format(self.packed))
+
+# Object for storing each gpio's config state
+
+class GPIOManager():
+ def __init__(self, dut, layout, wb_bus):
+ self.dut = dut
+ self.wb_bus = wb_bus
+ # arrangement of config bits making up csr word
+ self.csr_layout = layout
+ self.shift_dict = self._create_shift_dict()
+ self.n_gpios = len(self.dut.gpio_ports)
+ print(dir(self.dut))
+ # Since GPIO HDL block already has wordsize parameter, use directly
+ # Alternatively, can derive from WB data r/w buses (div by 8 for bytes)
+ #self.wordsize = len(self.dut.gpio_wb__dat_w) / 8
+ self.wordsize = self.dut.wordsize
+ self.n_rows = ceil(self.n_gpios / self.wordsize)
+ self.shadow_csr = []
+ for i in range(self.n_gpios):
+ self.shadow_csr.append(GPIOConfigReg(self.shift_dict))
+
+ def print_info(self):
+ print("----------")
+ print("GPIO Block Info:")
+ print("Number of GPIOs: {}".format(self.n_gpios))
+ print("WB Data bus width (in bytes): {}".format(self.wordsize))
+ print("Number of rows: {}".format(self.n_rows))
+ print("----------")
+
+ # The shifting of control bits in the configuration word is dependent on the
+ # defined layout. To prevent maintaining the shift constants in a separate
+ # location, the same layout is used to generate a dictionary of bit shifts
+ # with which the configuration word can be produced!
+ def _create_shift_dict(self):
+ shift = 0
+ shift_dict = {}
+ for i in range(0, len(self.csr_layout)):
+ shift_dict[self.csr_layout[i][0]] = shift
+ shift += self.csr_layout[i][1]
+ print(shift_dict)
+ return shift_dict
+
+ def _parse_gpio_arg(self, gpio_str):
+ # TODO: No input checking!
+ print("Given GPIO/range string: {}".format(gpio_str))
+ if gpio_str == "all":
+ start = 0
+ end = self.n_gpios
+ elif '-' in gpio_str:
+ start, end = gpio_str.split('-')
+ start = int(start)
+ end = int(end) + 1
+ if (end < start) or (end > self.n_gpios):
+ raise Exception("Second GPIO must be higher than first and"
+ + " must be lower or equal to last available GPIO.")
+ else:
+ start = int(gpio_str)
+ if start >= self.n_gpios:
+ raise Exception("GPIO must be less/equal to last GPIO.")
+ end = start + 1
+ print("Parsed GPIOs {0} until {1}".format(start, end))
+ return start, end
+
+ # Take a combined word and update shadow reg's
+ # TODO: convert hard-coded sizes to use the csrbus_layout (or dict?)
+ def update_single_shadow(self, csr_byte, gpio):
+ oe = (csr_byte >> self.shift_dict['oe']) & 0x1
+ ie = (csr_byte >> self.shift_dict['ie']) & 0x1
+ puen = (csr_byte >> self.shift_dict['puen']) & 0x1
+ pden = (csr_byte >> self.shift_dict['pden']) & 0x1
+ io = (csr_byte >> self.shift_dict['io']) & 0x1
+ bank = (csr_byte >> self.shift_dict['bank']) & 0x3
+
+ print("csr={0:x} | oe={1}, ie={2}, puen={3}, pden={4}, io={5}, bank={6}"
+ .format(csr_byte, oe, ie, puen, pden, io, bank))
+
+ self.shadow_csr[gpio].set(oe, ie, puen, pden, io, bank)
+ return oe, ie, puen, pden, io, bank
+
+ def rd_csr(self, row_start):
+ row_word = yield from wb_read(self.wb_bus, row_start)
+ print("Returned CSR: {0:x}".format(row_word))
+ return row_word
+
+ # Update a single row of configuration registers
+ def wr_row(self, row_addr, check=False):
+ curr_gpio = row_addr * self.wordsize
+ config_word = 0
+ for byte in range(0, self.wordsize):
+ if curr_gpio >= self.n_gpios:
+ break
+ config_word += self.shadow_csr[curr_gpio].packed << (8 * byte)
+ #print("Reading GPIO{} shadow reg".format(curr_gpio))
+ curr_gpio += 1
+ print("Writing shadow CSRs val {0:x} to row addr {1:x}"
+ .format(config_word, row_addr))
+ yield from wb_write(self.wb_bus, row_addr, config_word)
+ yield # Allow one clk cycle to propagate
+
+ if(check):
+ read_word = yield from self.rd_row(row_addr)
+ assert config_word == read_word
+
+ # Read a single address row of GPIO CSRs, and update shadow
+ def rd_row(self, row_addr):
+ read_word = yield from self.rd_csr(row_addr)
+ curr_gpio = row_addr * self.wordsize
+ single_csr = 0
+ for byte in range(0, self.wordsize):
+ if curr_gpio >= self.n_gpios:
+ break
+ single_csr = (read_word >> (8 * byte)) & 0xFF
+ #print("Updating GPIO{0} shadow reg to {1:x}"
+ # .format(curr_gpio, single_csr))
+ self.update_single_shadow(single_csr, curr_gpio)
+ curr_gpio += 1
+ return read_word
+
+ # Write all shadow registers to GPIO block
+ def wr_all(self, check=False):
+ for row in range(0, self.n_rows):
+ yield from self.wr_row(row, check)
+
+ # Read all GPIO block row addresses and update shadow reg's
+ def rd_all(self, check=False):
+ for row in range(0, self.n_rows):
+ yield from self.rd_row(row, check)
+
+ def config(self, gpio_str, oe, ie, puen, pden, outval, bank, check=False):
+ start, end = self._parse_gpio_arg(gpio_str)
+ # Update the shadow configuration
+ for gpio in range(start, end):
+ # print(oe, ie, puen, pden, outval, bank)
+ self.shadow_csr[gpio].set(oe, ie, puen, pden, outval, bank)
+ # TODO: only update the required rows?
+ yield from self.wr_all()
+
+ # Set/Clear the output bit for single or group of GPIOs
+ def set_out(self, gpio_str, outval):
+ start, end = self._parse_gpio_arg(gpio_str)
+ for gpio in range(start, end):
+ self.shadow_csr[gpio].set_out(outval)
+
+ if start == end:
+ print("Setting GPIO{0} output to {1}".format(start, outval))
+ else:
+ print("Setting GPIOs {0}-{1} output to {2}"
+ .format(start, end-1, outval))
+
+ yield from self.wr_all()
+
+ def rd_input(self, gpio_str): # REWORK
+ start, end = self._parse_gpio_arg(gpio_str)
+ curr_gpio = 0
+ # Too difficult to think about, just read all configs
+ #start_row = floor(start / self.wordsize)
+ # Hack because end corresponds to range limit, but maybe on same row
+ # TODO: clean
+ #end_row = floor( (end-1) / self.wordsize) + 1
+ read_data = [0] * self.n_rows
+ for row in range(0, self.n_rows):
+ read_data[row] = yield from self.rd_row(row)
+
+ num_to_read = (end - start)
+ read_in = [0] * num_to_read
+ curr_gpio = 0
+ for i in range(0, num_to_read):
+ read_in[i] = self.shadow_csr[curr_gpio].io
+ curr_gpio += 1
+
+ print("GPIOs {0} until {1}, i={2}".format(start, end, read_in))
+ return read_in
+
+ # TODO: There's probably a cleaner way to clear the bit...
+ def sim_set_in_pad(self, gpio_str, in_val):
+ start, end = self._parse_gpio_arg(gpio_str)
+ for gpio in range(start, end):
+ old_in_val = yield self.dut.gpio_ports[gpio].i
+ print(old_in_val)
+ print("GPIO{0} Previous i: {1:b} | New i: {2:b}"
+ .format(gpio, old_in_val, in_val))
+ yield self.dut.gpio_ports[gpio].i.eq(in_val)
+ yield # Allow one clk cycle to propagate
+
+ def rd_shadow(self):
+ shadow_csr = [0] * self.n_gpios
+ for gpio in range(0, self.n_gpios):
+ shadow_csr[gpio] = self.shadow_csr[gpio].packed
+
+ hex_str = ""
+ for reg in shadow_csr:
+ hex_str += " "+hex(reg)
+ print("Shadow reg's: ", hex_str)
+
+ return shadow_csr
projects / pinmux.git / blobdiff