test: add test_gearbox skeleton
[litex.git] / .gitmodules
index 07ef9c74a2611b6b894040cfdd0256fe7e49c312..11034c7d215343be4d659346b3a83e11a10ca652 100644 (file)
@@ -1,3 +1,12 @@
-[submodule "verilog/lm32/submodule"]
-       path = verilog/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+       path = litex/soc/cores/cpu/lm32/verilog/submodule
        url = https://github.com/m-labs/lm32.git
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+       path = litex/soc/cores/cpu/mor1kx/verilog
+       url = https://github.com/openrisc/mor1kx.git
+[submodule "litex/soc/software/compiler_rt"]
+       path = litex/soc/software/compiler_rt
+       url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+       path = litex/soc/cores/cpu/picorv32/verilog
+       url = https://github.com/cliffordwolf/picorv32