Merge pull request #412 from antmicro/fix-copyrights

[litex.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index 584a052deda78caea68496cf3b7b355a2ed9b618..2336869ef45b9cf20dacb5852ca3a22d201dcc06 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -6,7 +6,7 @@
        url = https://github.com/openrisc/mor1kx.git
 [submodule "litex/soc/software/compiler_rt"]
        path = litex/soc/software/compiler_rt
-       url = http://llvm.org/git/compiler-rt.git
+       url = https://git.llvm.org/git/compiler-rt
 [submodule "litex/soc/cores/cpu/picorv32/verilog"]
        path = litex/soc/cores/cpu/picorv32/verilog
        url = https://github.com/cliffordwolf/picorv32
@@ -15,4 +15,16 @@
        url = https://github.com/enjoy-digital/tapcfg
 [submodule "litex/soc/cores/cpu/vexriscv/verilog"]
        path = litex/soc/cores/cpu/vexriscv/verilog
-       url = https://github.com/m-labs/VexRiscv-verilog.git
+       url = https://github.com/enjoy-digital/VexRiscv-verilog.git
+[submodule "litex/soc/cores/cpu/minerva/verilog"]
+       path = litex/soc/cores/cpu/minerva/verilog
+       url = https://github.com/lambdaconcept/minerva
+[submodule "litex/soc/cores/cpu/rocket/verilog"]
+       path = litex/soc/cores/cpu/rocket/verilog
+       url = https://github.com/enjoy-digital/rocket-litex-verilog
+[submodule "litex/soc/cores/cpu/microwatt/sources"]
+       path = litex/soc/cores/cpu/microwatt/sources
+       url = https://github.com/antonblanchard/microwatt
+[submodule "litex/soc/cores/cpu/blackparrot/pre-alpha-release"]
+       path = litex/soc/cores/cpu/blackparrot/pre-alpha-release
+       url = https://github.com/enjoy-digital/black-parrot.git