[submodule "litex/soc/cores/cpu/picorv32/verilog"]
path = litex/soc/cores/cpu/picorv32/verilog
url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+ path = litex/build/sim/core/modules/ethernet/tapcfg
+ url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+ path = litex/soc/cores/cpu/vexriscv/verilog
+ url = https://github.com/m-labs/VexRiscv-verilog.git