platforms/versa_ecp5: import migen changes

[litex.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index 4c401e1a9bcf5c9ebe4b8f17e8a6713b5d9fc2cd..26af8537e81648def9d1cdbb5059ba3b7fc4f5cd 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -7,3 +7,12 @@
 [submodule "litex/soc/software/compiler_rt"]
        path = litex/soc/software/compiler_rt
        url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+       path = litex/soc/cores/cpu/picorv32/verilog
+       url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+       path = litex/build/sim/core/modules/ethernet/tapcfg
+       url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+       path = litex/soc/cores/cpu/vexriscv/verilog
+       url = https://github.com/m-labs/VexRiscv-verilog.git