soc/cores/clock: different vco_freq_range for pll and mmcm

[litex.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index a952646d16d0a985e90407b5975b9355aa273ea1..26af8537e81648def9d1cdbb5059ba3b7fc4f5cd 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,18 @@
-[submodule "verilog/lm32/submodule"]
-       path = verilog/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+       path = litex/soc/cores/cpu/lm32/verilog/submodule
        url = https://github.com/m-labs/lm32.git
-[submodule "verilog/mor1kx/submodule"]
-       path = verilog/mor1kx/submodule
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+       path = litex/soc/cores/cpu/mor1kx/verilog
        url = https://github.com/openrisc/mor1kx.git
-[submodule "software/compiler-rt"]
-       path = software/compiler-rt
+[submodule "litex/soc/software/compiler_rt"]
+       path = litex/soc/software/compiler_rt
        url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+       path = litex/soc/cores/cpu/picorv32/verilog
+       url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+       path = litex/build/sim/core/modules/ethernet/tapcfg
+       url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+       path = litex/soc/cores/cpu/vexriscv/verilog
+       url = https://github.com/m-labs/VexRiscv-verilog.git