-[submodule "extcores/lm32/submodule"]
- path = extcores/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+ path = litex/soc/cores/cpu/lm32/verilog/submodule
url = https://github.com/m-labs/lm32.git
-[submodule "extcores/mor1kx/submodule"]
- path = extcores/mor1kx/submodule
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+ path = litex/soc/cores/cpu/mor1kx/verilog
url = https://github.com/openrisc/mor1kx.git
-[submodule "software/compiler-rt"]
- path = software/compiler-rt
+[submodule "litex/soc/software/compiler_rt"]
+ path = litex/soc/software/compiler_rt
url = http://llvm.org/git/compiler-rt.git
-[submodule "extcores/litepcie_phy_wrappers"]
- path = extcores/litepcie_phy_wrappers
- url = https://github.com/enjoy-digital/litepcie_phy_wrappers
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+ path = litex/soc/cores/cpu/picorv32/verilog
+ url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+ path = litex/build/sim/core/modules/ethernet/tapcfg
+ url = https://github.com/nizox/tapcfg
+[submodule "litex/soc/cores/cpu/vexriscv/verilog"]
+ path = litex/soc/cores/cpu/vexriscv/verilog
+ url = https://github.com/m-labs/VexRiscv-verilog.git