gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal...

[litex.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index 9b5c03e8a5801f835bd1695dd58359e6659d825f..4c401e1a9bcf5c9ebe4b8f17e8a6713b5d9fc2cd 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,12 +1,9 @@
-[submodule "misoc/cores/lm32/verilog/submodule"]
-       path = misoc/cores/lm32/verilog/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+       path = litex/soc/cores/cpu/lm32/verilog/submodule
        url = https://github.com/m-labs/lm32.git
-[submodule "misoc/cores/mor1kx/verilog"]
-       path = misoc/cores/mor1kx/verilog
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+       path = litex/soc/cores/cpu/mor1kx/verilog
        url = https://github.com/openrisc/mor1kx.git
-[submodule "misoc/software/compiler_rt"]
-       path = misoc/software/compiler_rt
+[submodule "litex/soc/software/compiler_rt"]
+       path = litex/soc/software/compiler_rt
        url = http://llvm.org/git/compiler-rt.git
-[submodule "misoc/software/unwinder"]
-       path = misoc/software/unwinder
-       url = https://github.com/whitequark/libunwind