-[submodule "verilog/lm32/submodule"]
- path = verilog/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+ path = litex/soc/cores/cpu/lm32/verilog/submodule
url = https://github.com/m-labs/lm32.git
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+ path = litex/soc/cores/cpu/mor1kx/verilog
+ url = https://github.com/openrisc/mor1kx.git
+[submodule "litex/soc/software/compiler_rt"]
+ path = litex/soc/software/compiler_rt
+ url = http://llvm.org/git/compiler-rt.git