Change the default IRQs.

[litex.git] / .gitmodules

diff --git a/.gitmodules b/.gitmodules
index 41a166d11195e4d616a10be35a300c181c7b4cd0..69988365be41d1345c7a1543c44eab3c4acaf17e 100644 (file)
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +1,15 @@
-[submodule "verilog/lm32/submodule"]
-       path = verilog/lm32/submodule
+[submodule "litex/soc/cores/cpu/lm32/verilog/submodule"]
+       path = litex/soc/cores/cpu/lm32/verilog/submodule
        url = https://github.com/m-labs/lm32.git
-[submodule "verilog/mor1kx/submodule"]
-       path = verilog/mor1kx/submodule
+[submodule "litex/soc/cores/cpu/mor1kx/verilog"]
+       path = litex/soc/cores/cpu/mor1kx/verilog
        url = https://github.com/openrisc/mor1kx.git
+[submodule "litex/soc/software/compiler_rt"]
+       path = litex/soc/software/compiler_rt
+       url = http://llvm.org/git/compiler-rt.git
+[submodule "litex/soc/cores/cpu/picorv32/verilog"]
+       path = litex/soc/cores/cpu/picorv32/verilog
+       url = https://github.com/cliffordwolf/picorv32
+[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
+       path = litex/build/sim/core/modules/ethernet/tapcfg
+       url = https://github.com/nizox/tapcfg