targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll
[litex.git] / .travis-build-socs.sh
index 2e3c274bd4fda15b6ac669edb9bd6c0fea5a30f2..54cd4301f02e21440f7c29988dca8202b464b3a2 100755 (executable)
@@ -2,16 +2,27 @@
 
 set -e
 
+# Some colors, use it like following;
+# echo -e "Hello ${YELLOW}yellow${NC}"
+GRAY='\033[0;30m'
+GREEN='\033[0;32m'
+YELLOW='\033[0;33m'
+PURPLE='\033[0;35m'
+NC='\033[0m' # No Color
+
+SPACER="echo -e ${GRAY} - ${NC}"
+
 travis_fold start "environment.create"
 travis_time_start
-echo "Setting up basic conda environment"
+echo -e "Setting up basic ${YELLOW}conda environment${NC}"
 echo "-------------------------------------------------------------------"
 conda env create -f environment.yml
 source activate litex
 echo "-------------------------------------------------------------------"
 travis_time_finish
 travis_fold end "environment.create"
-echo "-"
+
+$SPACER
 
 SOC_FILES=$(find litex/boards/targets -name \*.py | grep -v sim | grep -v "__")
 
@@ -23,17 +34,18 @@ for SOC_FILE in $SOC_FILES; do
 
        travis_fold start "$SOC.1"
        travis_time_start
-       echo "Building $TARGET ($SOC)"
+       echo -e "Building ${GREEN}${TARGET}${NC} (${PURPLE}${SOC}${NC})"
        echo "-------------------------------------------------------------------"
        python -m $SOC --no-compile-gateware
        echo "-------------------------------------------------------------------"
        travis_time_finish
        travis_fold end "$SOC.1"
        travis_fold start "$SOC.2"
-       echo "Output of building $SOC"
+       echo -e "Output of building ${GREEN}${TARGET}${NC} (${PURPLE}${SOC}${NC})"
        echo "-------------------------------------------------------------------"
        find soc_*$TARGET* | sort
        echo "-------------------------------------------------------------------"
        travis_fold end "$SOC.2"
-       echo "-"
+
+       $SPACER
 done