platforms/kcu105: set internal vref on ddr4 banks

[litex.git] / .travis.yml

diff --git a/.travis.yml b/.travis.yml
index bb0b0d8ff85222025878a32d3d73b00ca9b240da..f870e95e007201afe6f1e804c802945f4fb5914c 100644 (file)
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,15 +1,19 @@
 language: python
 python:
-  - "3.4"
+ - "3.6"
 
 install:
-  # Install iverilog package.
-  - "sudo add-apt-repository -y ppa:mithro/iverilog-backport"
-  - "sudo apt-get update"
-  - "sudo apt-get install iverilog"
-  - "iverilog -v; true"
-  # Build the vpi module.
-  - "(cd vpi; make; sudo make install)"
+ - wget https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O miniconda.sh
+ - bash miniconda.sh -b -p $HOME/miniconda
+ - export PATH="$HOME/miniconda/bin:$PATH"
+ - hash -r
+ - conda config --set always_yes yes --set changeps1 no
+
+before_script:
+ - export -f travis_nanoseconds
+ - export -f travis_fold
+ - export -f travis_time_start
+ - export -f travis_time_finish
 
 script:
-  - "python setup.py test"
+ - ./.travis-build-socs.sh