cores/cpu/microwatt: revert setup stack and fix missing subi %r1,%r1,0x100 (thanks...

[litex.git] / CHANGES

diff --git a/CHANGES b/CHANGES
index f4b28cd8ad9f1544ccbe6af470d503ae30637a1b..9e4ab49e7587afd0708e4bf498ecb0c121abd910 100644 (file)
--- a/CHANGES
+++ b/CHANGES
@@ -7,15 +7,31 @@
 
        [> Added Features
        ------------------
-       - BIOS history, autocomplete.
-       - Pluggable CPUs.
-       - Add nMigen dependency.
        - Properly integrate Minerva CPU.
+       - Add nMigen dependency.
+       - Pluggable CPUs.
+       - BIOS history, autocomplete.
+       - Improve boards's programmers.
+       - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
+       - Speedup Memtest using an LFSR.
+       - Add LedChaser on boards.
+       - Improve WishboneBridge.
+       - Improve Diamond constraints.
+       - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
+       - Add CV32E40P CPU support (ex RI5CY).
+       - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
+       - Add Symbiflow experimental support on Arty.
+       - Add SDCard boot from FAT/exFAT filesystems with FatFs.
+       - Simplify boot with boot.json configuration file.
 
        [> API changes/Deprecation
        --------------------------
-       - NA
-
+       - Add --build --load arguments to targets.
+       - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
+       - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
+       - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
+       - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
+       - Rename --gateware-toolchain target parameter to --toolchain.
 
 [> 2020.04, released April 28th, 2020
 -------------------------------------