[> Issues resolved
------------------
- Fix flush_cpu_icache on VexRiscv.
+ - Fix `.data` section placed in rom (#566)
[> Added Features
------------------
- - BIOS history, autocomplete.
- - Pluggable CPUs.
- - Add nMigen dependency.
- Properly integrate Minerva CPU.
+ - Add nMigen dependency.
+ - Pluggable CPUs.
+ - BIOS history, autocomplete.
+ - Improve boards's programmers.
+ - Add Microwatt CPU support (with GHDL-Yosys-plugin support for FOSS toolchains).
+ - Speedup Memtest using an LFSR.
+ - Add LedChaser on boards.
+ - Improve WishboneBridge.
+ - Improve Diamond constraints.
+ - Use InterconnectPointToPoint when 1 master,1 slave and no address translation.
+ - Add CV32E40P CPU support (ex RI5CY).
+ - JTAG UART with uart_name=jtag_uart (validated on Spartan6, 7-Series, Ultrascale(+)).
+ - Add Symbiflow experimental support on Arty.
+ - Add SDCard boot from FAT/exFAT filesystems with FatFs.
+ - Simplify boot with boot.json configuration file.
+ - Revert to a single crt0 (avoid ctr/xip variants).
[> API changes/Deprecation
--------------------------
- - NA
-
+ - Add --build --load arguments to targets.
+ - Deprecate soc.interconnect.wishbone.UpConverter (will be rewritten if useful).
+ - Deprecate soc.interconnect.wishbone.CSRBank (Does not seem to be used by anyone).
+ - Move soc.interconnect.wishbone2csr.WB2CSR to soc.interconnect.wishbone.Wishbone2CSR.
+ - Move soc.interconnect.wishbonebridge.WishboneStreamingBridge to soc.cores.uart.Stream2Wishbone.
+ - Rename --gateware-toolchain target parameter to --toolchain.
[> 2020.04, released April 28th, 2020
-------------------------------------