Add verilog submodule from CPU cores to manifest

[litex.git] / MANIFEST.in

diff --git a/MANIFEST.in b/MANIFEST.in
index 26d681702c6a9e299be7a3277b8092d6e203461b..a15c845d9f3fc56902858006bbc483e8e22ecefe 100644 (file)
--- a/MANIFEST.in
+++ b/MANIFEST.in
@@ -1,5 +1,8 @@
 graft litex/build/sim
 graft litex/soc/software
 graft litex/soc/cores/cpu/lm32/verilog
+graft litex/soc/cores/cpu/minerva/verilog
 graft litex/soc/cores/cpu/mor1kx/verilog
-graft litex/soc/cores/cpu/picorv32/verilog
\ No newline at end of file
+graft litex/soc/cores/cpu/picorv32/verilog
+graft litex/soc/cores/cpu/rocket/verilog
+graft litex/soc/cores/cpu/vexriscv/verilog