targets: add versa_ecp5 with sdram (ecp5 soc hat) at 25MHz/no pll

[litex.git] / README

diff --git a/README b/README
index 0f6d2521b0fff29992774f6f74b854f8e766cc52..388858ca6eaa61709a8a4e7f436739237a0235af 100644 (file)
--- a/README
+++ b/README
@@ -9,9 +9,18 @@
 
 [> Intro
 --------
-LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
-our cores, integrate them in complete SoC and load/flash them to the hardware
-and experiment new features.
+LiteX is a FPGA design/SoC builder that can be used to build cores, create
+SoCs and full FPGA designs.
+
+LiteX is based on Migen and provides specific building/debugging tools for
+a higher level of abstraction and compatibily with the LiteX core ecosystem.
+
+Think of Migen as a toolbox to create FPGA designs in Python and LiteX as a
+toolbox to create/develop/debug FPGA SoCs in Python.
+
+
+Typical LiteX design flow:
+--------------------------
 
                         +---------------+
                         |FPGA toolchains|
@@ -26,14 +35,26 @@ and experiment new features.
 +----------------------+  |           |
 |LiteX Cores Ecosystem +-->           |
 +----------------------+  +-^-------^-+
- (Eth,,SATA,,DRAM,,USB,     |       |
-  PCIe,Video,etc...)        +       +
+ (Eth, SATA, DRAM, USB,     |       |
+  PCIe, Video, etc...)      +       +
                            board   target
                            file    file
 
 
-The structure of LiteX is kept close to MiSoC to ease collaboration between
-projects.
+LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
+and is compatible with the LiteX's Cores Ecosystem:
+
+- LiteDRAM: https://github.com/enjoy-digital/litedram
+- LiteEth: https://github.com/enjoy-digital/liteeth
+- LitePCIe: https://github.com/enjoy-digital/litepcie
+- LiteSATA: https://github.com/enjoy-digital/litesata
+- LiteUSB: https://github.com/enjoy-digital/liteusb
+- LiteSDCard: https://github.com/enjoy-digital/litesdcard
+- LiteICLink: https://github.com/enjoy-digital/liteiclink
+- LiteJESD204B: https://github.com/enjoy-digital/litejesd204b
+- LiteVideo: https://github.com/enjoy-digital/litevideo
+- LiteScope: https://github.com/enjoy-digital/litescope
+
 
 [> Sub-packages
 ---------------
@@ -50,14 +71,49 @@ soc:
   to build a SoC from such cores.
 
 boards:
-  Provides platforms and targets for the supported boards.
+  Provides platforms and targets for the supported boards. All Migen's platforms
+  can also be used in LiteX.
+
+[> Very Quick start guide (for newcomers)
+-----------------------------------------
+TimVideos.us has done an awesome job for setting up a LiteX environment easily in
+the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
+
+It's recommended for newcomers to go this way. Various FPGA boards are supported
+and multiple examples provided! You can even run Linux on your FPGA using LiteX
+very easily!
+
+Migen documentation can be found here: https://m-labs.hk/migen/manual
+
+FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_101
+
+[> Medium Quick start guide with Conda
+-----------------------------------------
+
+0. Get miniconda by following instructions at https://conda.io/miniconda.html
+
+1. Clone LiteX
+  git clone --recurse-submodules https://github.com/enjoy-digital/litex.git
+
+2. Create a LiteX environment from environment.yml
+  conda env create -f environment.yml
+
+3. Enter conda environment
+  conda activate litex
+
+4. Build the target of your board...:
+  Go to boards/targets and execute the target you want to build
+
 
-[> Quick start guide
---------------------
-0. If cloned from Git without the --recursive option, get the submodules:
-  git submodule update --init
+[> Quick start guide (for advanced users)
+-----------------------------------------
+0. Install Python 3.5+ and FPGA vendor's development tools.
 
-1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
+1. Get litex_setup.py script and execute:
+   ./litex_setup.py init install
+   This will clone and install Migen, LiteX and LiteX's cores.
+   To update all repositories execute:
+   ./litex_setup.py update
 
 2. Compile and install binutils. Take the latest version from GNU.
   mkdir build && cd build
@@ -80,13 +136,15 @@ boards:
 
 5. ... and/or install Verilator and test LiteX on your computer:
   Download and install Verilator: http://www.veripool.org/
-  Install libevent-devel / json-c-devel packages
-  Go to boards/targets
-  ./sim.py
+  On Fedora:
+      sudo dnf install libevent-devel json-c-devel
+  On Ubuntu:
+      sudo apt install libevent-dev libjson-c-dev
+  run: litex_sim
 
 6. Run a terminal program on the board's serial port at 115200 8-N-1.
   You should get the BIOS prompt.
 
 [> Contact
 ----------
-E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file
+E-mail: florent [AT] enjoy-digital.fr