gen: add common with reverse_bits/reverse_bytes functions

[litex.git] / README

diff --git a/README b/README
index e167f55b6f287e903ccc12ee39469c0502e13ba2..388858ca6eaa61709a8a4e7f436739237a0235af 100644 (file)
--- a/README
+++ b/README
@@ -136,9 +136,11 @@ FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_10
 
 5. ... and/or install Verilator and test LiteX on your computer:
   Download and install Verilator: http://www.veripool.org/
-  Install libevent-devel / json-c-devel packages
-  Go to boards/targets
-  ./sim.py
+  On Fedora:
+      sudo dnf install libevent-devel json-c-devel
+  On Ubuntu:
+      sudo apt install libevent-dev libjson-c-dev
+  run: litex_sim
 
 6. Run a terminal program on the board's serial port at 115200 8-N-1.
   You should get the BIOS prompt.