gen/genlib/cdc/gearbox: fix possible pointers overlap by removing AsyncResetSynchroni...

[litex.git] / README

diff --git a/README b/README
index b11280616190467ab867003c05cc4d2077590075..38f15ce6ded47fffe6d25ad709bf6432df07c4cc 100644 (file)
--- a/README
+++ b/README
@@ -2,29 +2,32 @@
                       / /  (_) /____ | |/_/
                      / /__/ / __/ -_)>  <
                     /____/_/\__/\__/_/|_|
+                         Migen inside
 
                 Build your hardware, easily!
-                Copyright 2015 Enjoy-Digital
+             Copyright 2012-2016 Enjoy-Digital
 
 [> Intro
----------
-LiteX is an alternative (fork) to Migen/MiSoC maintained and used by Enjoy-Digital
-to build our cores, integrate them in complete SoC and load/flash them to the
-hardware.
+--------
+LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
+to build our cores, integrate them in complete SoC and load/flash them to
+the hardware and experiment new features.
 
 The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
-between projects.
+between projects and efforts are made to keep cores developed with LiteX
+compatible with Migen/MiSoC.
 
 [> License
------------
-LiteX is copyright (c) 2015 Enjoy-Digital under BSD Lisense.
-Since it is based on MiSoC/Migen, please also refer to LICENSE files in soc/gen 
-directories or git history to get correct copyrights.
+----------
+LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
+Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
+directory or git history to get correct copyrights.
 
 [> Sub-packages
------------
+---------------
 gen:
-  Provides tools and simple modules to generate HDL.
+  Provides specific or experimentatl modules to generate HDL that are not integrated
+  in Migen.
 
 build:
   Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
@@ -42,7 +45,8 @@ boards:
 0. If cloned from Git without the --recursive option, get the submodules:
   git submodule update --init
 
-1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
+1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
+  Get Migen from: https://github.com/m-labs/migen
 
 2. Compile and install binutils. Take the latest version from GNU.
   mkdir build && cd build
@@ -65,6 +69,7 @@ boards:
 
 5. ... and/or install Verilator and test LiteX on your computer:
   Download and install Verilator: http://www.veripool.org/
+  Install libevent-devel / json-c-devel packages
   Go to boards/targets
   ./sim.py
 
@@ -72,4 +77,5 @@ boards:
   You should get the BIOS prompt.
 
 [> Contact
+----------
 E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file