- __ ___ _ ____ _____
- / |/ / (_) / __/__ / ___/
- / /|_/ / / / _\ \/ _ \/ /__
- /_/ /_/ /_/ /___/\___/\___/
-
- Copyright 2007-2015 / M-Labs Ltd
- Copyright 2012-2015 / Enjoy-Digital
-
- a high performance and small footprint SoC based on Migen
-
-[> Features
------------
- * LatticeMico32 CPU, modified to include an optional MMU (experimental).
- * mor1kx (a better OpenRISC implementation) as alternative CPU option.
- * High performance memory controller capable of issuing several SDRAM commands
- per FPGA cycle.
- * Supports SDR, DDR, LPDDR, DDR2 and DDR3.
- * Provided peripherals: UART, GPIO, timer, GPIO, NOR flash controller, SPI
- flash controller, Ethernet MAC, and more.
- * High performance:
- - on Spartan-6, 83MHz system clock frequencies, 10+Gbps DDR
- SDRAM bandwidth, 1080p 32bpp framebuffer, etc.
- - on Kintex-7, 125MHz system clock frequencies (up to 200MHz without DDR3),
- 64Gbps DDR3 SDRAM bandwidth.
- * Low resource usage: basic implementation fits easily in Spartan-6 LX9.
- * Portable and easy to customize thanks to Python- and Migen-based
- architecture.
- * Design new peripherals using Migen and benefit from automatic CSR maps
- and logic, etc.
- * Possibility to encapsulate legacy Verilog/VHDL code.
- * Complex FPGA cores that can be used integrated in MiSoC or standalone:
- - LiteEth: a small footprint and configurable Ethernet core
-
-MiSoC comes with built-in support for the following boards:
- * Mixxeo, the digital video mixer from M-Labs [XC6SLX45]
- * Milkymist One, the original M-Labs video synthesizer [XC6SLX45]
- * Papilio Pro, a simple and low-cost development board [XC6SLX9]
- * Pipistrello, a simple board with USB and HDMI [XC6SLX45]
- * De0 Nano, a simple and low-cost development board [CYCLONEIV]
- * KC705, a Kintex-7 devboard from Xilinx [XC7K325T]
- * Versa, a low-cost Lattice development board [ECP3-35]
-MiSoC is portable and support for other boards can easily be added as external
-modules.
-
-[> Quick start guide
---------------------
-0. If cloned from Git without the --recursive option, get the submodules:
- git submodule update --init
-
-1. Install Python 3.3+, Migen and FPGA vendor's development tools.
- Get Migen from: https://github.com/m-labs/migen
-
-2. Install JTAG tools.
- For Mixxeo and M1: http://urjtag.org
- For Papilio Pro and KC705: http://xc3sprog.sourceforge.net
- For De0 Nano: USBBlaster from Altera
- We recommend using xc3sprog for Xilinx devices, but Vivado programmer
- is also supported for Xilinx 7-series.
-
-3. (Optional, only needed if you want to flash the bistream/software)
- Obtain and build any required flash proxy bitstreams. Flash proxy bitstreams
- give JTAG access to a flash chip through the FPGA.
- For Mixxeo and M1: https://github.com/m-labs/fjmem-m1
- For Papilio Pro: https://github.com/GadgetFactory/Papilio-Loader
- (xc3sprog/trunk/bscan_spi/bscan_spi_lx9_papilio.bit)
- For KC705: https://github.com/m-labs/bscan_spi_kc705
-
-4. Compile and install binutils. Take the latest version from GNU.
+ __ _ __ _ __
+ / / (_) /____ | |/_/
+ / /__/ / __/ -_)> <
+ /____/_/\__/\__/_/|_|
+ Migen inside
+
+ Build your hardware, easily!
+ Copyright 2012-2018 / EnjoyDigital
+
+[> Intro
+--------
+LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
+our cores, integrate them in complete SoC and load/flash them to the hardware
+and experiment new features. (structure is kept close to MiSoC to ease
+collaboration)
+
+Typical LiteX design flow:
+--------------------------
+
+ +---------------+
+ |FPGA toolchains|
+ +----^-----+----+
+ | |
+ +--+-----v--+
+ +-------+ | |
+ | Migen +--------> |
+ +-------+ | | Your design
+ | LiteX +---> ready to be used!
+ | |
++----------------------+ | |
+|LiteX Cores Ecosystem +--> |
++----------------------+ +-^-------^-+
+ (Eth, SATA, DRAM, USB, | |
+ PCIe, Video, etc...) + +
+ board target
+ file file
+
+
+LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
+and is compatible with the LiteX's Cores Ecosystem:
+
+- LiteDRAM: https://github.com/enjoy-digital/litedram
+- LiteEth: https://github.com/enjoy-digital/liteeth
+- LitePCIe: https://github.com/enjoy-digital/litepcie
+- LiteSATA: https://github.com/enjoy-digital/litesata
+- LiteUSB: https://github.com/enjoy-digital/litesata
+- LiteSDCard: https://github.com/enjoy-digital/litesdcard
+- LiteICLink: https://github.com/enjoy-digital/liteiclink
+- LiteJESD204B: https://github.com/enjoy-digital/litejesd204b
+- LiteVideo: https://github.com/enjoy-digital/litevideo
+- LiteScope: https://github.com/enjoy-digital/litescope
+
+
+[> Sub-packages
+---------------
+gen:
+ Provides specific or experimental modules to generate HDL that are not integrated
+ in Migen.
+
+build:
+ Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
+ simulate HDL code or full SoCs.
+
+soc:
+ Provides definitions/modules to build cores (bus, bank, flow), cores and tools
+ to build a SoC from such cores.
+
+boards:
+ Provides platforms and targets for the supported boards. All Migen's platforms
+ can also be used in LiteX.
+
+[> Very Quick start guide (for newcomers)
+-----------------------------------------
+TimVideos.us has done an awesome job for setting up a LiteX environment easily in
+the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
+
+It's recommended for newcomers to go this way. Various FPGA boards are supported
+and multiple examples provided! You can even run Linux on your FPGA using LiteX
+very easily!
+
+Migen documentation can be found here: https://m-labs.hk/migen/manual
+
+FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_101
+
+[> Medium Quick start guide with Conda
+-----------------------------------------
+
+0. Get miniconda by following instructions at https://conda.io/miniconda.html
+
+1. Clone LiteX
+ git clone --recurse-submodules https://github.com/enjoy-digital/litex.git
+
+2. Create a LiteX environment from environment.yml
+ conda env create -f environment.yml
+
+3. Enter conda environment
+ conda activate litex
+
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
+
+
+[> Quick start guide (for advanced users)
+-----------------------------------------
+0. Install Python 3.5+ and FPGA vendor's development tools.
+
+1. Get litex_setup.py script and execute:
+ ./litex_setup.py init install
+ This will clone and install Migen, LiteX and LiteX's cores.
+ To update all repositories execute:
+ ./litex_setup.py update
+
+2. Compile and install binutils. Take the latest version from GNU.
mkdir build && cd build
../configure --target=lm32-elf
make
make install
-5. Compile and install GCC. Take gcc-core and gcc-g++ from GNU
+3. (Optional, only if you want to use a lm32 CPU in you SoC)
+ Compile and install GCC. Take gcc-core and gcc-g++ from GNU
(version 4.5 or >=4.9).
rm -rf libstdc++-v3
mkdir build && cd build
make
make install
-6. Build and flash the BIOS and bitstream. Run from MiSoC:
- For Mixxeo: ./make.py all
- For M1: ./make.py -p m1 all
- For Papilio Pro: ./make.py -t ppro all
- For Pipistrello: ./make.py -t pipistrello all
- For De0 Nano: ./make.py -t de0nano all load-bitstream
- For KC705: ./make.py -t kc705 all
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
- If just want to load the bitstream in volatile SRAM use:
- all load-bitstream
+5. ... and/or install Verilator and test LiteX on your computer:
+ Download and install Verilator: http://www.veripool.org/
+ Install libevent-devel / json-c-devel packages
+ Go to boards/targets
+ ./sim.py
-7. Run a terminal program on the board's serial port at 115200 8-N-1.
+6. Run a terminal program on the board's serial port at 115200 8-N-1.
You should get the BIOS prompt.
-8. Read and experiment with the source!
- Come to our IRC channel and mailing list!
- A simple target is provided to test MiSoC easily with your board:
- Create your target with a clock and serial pins.
- Build and test it: ./make.py -t simple -p your_platform all load-bitstream
- If you don't have access to a FPGA board, you can also try MiSoC
- with Verilator:
- Download and install Verilator: http://www.veripool.org/
- Test it: ./make.py -t simple -p sim build-bitstream
-
-9. Contribute a patch!
- Once you have experimented with stuff, please send your results back.
- For more details on how to do so, you can see the CONTRIBUTING.rst file.
-
-[> License
+[> Contact
----------
-MiSoC is released under the very permissive two-clause BSD license. Under
-the terms of this license, you are authorized to use MiSoC for
-closed-source proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- * tell us that you are using MiSoC
- * cite MiSoC in publications related to research it has helped
- * send us feedback and suggestions for improvements
- * send us bug reports when something goes wrong
- * send us the modifications and improvements you have done to MiSoC.
- The use of "git format-patch" is recommended. If your submission is large
- and complex and/or you are not sure how to proceed, feel free to discuss it
- on the mailing list or IRC (#m-labs on Freenode) beforehand.
-
-See LICENSE file for full copyright and license info.
-
-[> Links
---------
-Web:
- http://m-labs.hk
- http://enjoy-digital.fr
-
-Code repository:
- https://github.com/m-labs/misoc
-
-You can contact us on the public mailing list devel [AT] lists.m-labs.hk.
+E-mail: florent [AT] enjoy-digital.fr
projects / litex.git / blobdiff