-Migen (Milkymist Generator)
- a Python toolbox for building complex digital hardware
-
-Despite being faster than schematics entry, hardware design with Verilog and
-VHDL remains tedious and inefficient for several reasons. The event-driven
-model introduces issues and manual coding that are unnecessary for synchronous
-circuits, which represent the lion's share of today's logic designs. Counter-
-intuitive arithmetic rules result in steeper learning curves and provide a
-fertile ground for subtle bugs in designs. Finally, support for procedural
-generation of logic (metaprogramming) through "generate" statements is very
-limited and restricts the ways code can be made generic, reused and organized.
-
-To address those issues, we have developed the Migen FHDL library that
-replaces the event-driven paradigm with the notions of combinatorial and
-synchronous statements, has arithmetic rules that make integers always behave
-like mathematical integers, and most importantly allows the design's logic to
-be constructed by a Python program. This last point enables hardware designers
-to take advantage of the richness of the Python language - object oriented
-programming, function parameters, generators, operator overloading, libraries,
-etc. - to build well organized, reusable and elegant designs.
-
-Other Migen libraries are built on FHDL and provide various tools such as a
-system-on-chip interconnect infrastructure, a dataflow programming system, a
-more traditional high-level synthesizer that compiles Python routines into
-state machines with datapaths, and a simulator that allows test benches to be
-written in Python.
-
-Migen is the foundation of the next-generation Milkymist SoC.
-
-See the doc/ folder for more technical information.
-
-Code repository:
-https://github.com/milkymist/migen
-New Milkymist SoC based on Migen:
-https://github.com/milkymist/milkymist-ng
-
-Migen is designed for Python 3.3.
-
-Migen is released under the very permissive two-clause BSD license. Under the
-terms of this license, you are authorized to use Migen for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- * tell us that you are using Migen
- * put the Migen logo (doc/migen_logo.svg) on the page of a product using it,
- with a link to milkymist.org
- * cite Migen in publications related to research it has helped
- * send us feedback and suggestions for improvements
- * send us bug reports when something goes wrong
- * send us the modifications and improvements you have done to Migen. The use
- of "git format-patch" is recommended. If your submission is large and
- complex and/or you are not sure how to proceed, feel free to discuss it on
- the mailing list or IRC (#milkymist on Freenode) beforehand.
-
-See LICENSE file for full copyright and license info. You can contact us on the
-public mailing list devel [AT] lists.milkymist.org.
-
- "Electricity! It's like magic!"
+ __ _ __ _ __
+ / / (_) /____ | |/_/
+ / /__/ / __/ -_)> <
+ /____/_/\__/\__/_/|_|
+ Migen inside
+
+ Build your hardware, easily!
+ Copyright 2012-2018 / EnjoyDigital
+
+[> Intro
+--------
+LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
+our cores, integrate them in complete SoC and load/flash them to the hardware
+and experiment new features. (structure is kept close to MiSoC to ease
+collaboration)
+
+Typical LiteX design flow:
+--------------------------
+
+ +---------------+
+ |FPGA toolchains|
+ +----^-----+----+
+ | |
+ +--+-----v--+
+ +-------+ | |
+ | Migen +--------> |
+ +-------+ | | Your design
+ | LiteX +---> ready to be used!
+ | |
++----------------------+ | |
+|LiteX Cores Ecosystem +--> |
++----------------------+ +-^-------^-+
+ (Eth, SATA, DRAM, USB, | |
+ PCIe, Video, etc...) + +
+ board target
+ file file
+
+
+LiteX already supports various softcores CPUs: LM32, Mor1kx, PicoRV32, VexRiscv
+and is compatible with the LiteX's Cores Ecosystem:
+
+- LiteDRAM: https://github.com/enjoy-digital/litedram
+- LiteEth: https://github.com/enjoy-digital/liteeth
+- LitePCIe: https://github.com/enjoy-digital/litepcie
+- LiteSATA: https://github.com/enjoy-digital/litesata
+- LiteUSB: https://github.com/enjoy-digital/litesata
+- LiteSDCard: https://github.com/enjoy-digital/litesdcard
+- LiteICLink: https://github.com/enjoy-digital/liteiclink
+- LiteJESD204B: https://github.com/enjoy-digital/litejesd204b
+- LiteVideo: https://github.com/enjoy-digital/litevideo
+- LiteScope: https://github.com/enjoy-digital/litescope
+
+
+[> Sub-packages
+---------------
+gen:
+ Provides specific or experimental modules to generate HDL that are not integrated
+ in Migen.
+
+build:
+ Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
+ simulate HDL code or full SoCs.
+
+soc:
+ Provides definitions/modules to build cores (bus, bank, flow), cores and tools
+ to build a SoC from such cores.
+
+boards:
+ Provides platforms and targets for the supported boards. All Migen's platforms
+ can also be used in LiteX.
+
+[> Very Quick start guide (for newcomers)
+-----------------------------------------
+TimVideos.us has done an awesome job for setting up a LiteX environment easily in
+the litex-buildenv repo: https://github.com/timvideos/litex-buildenv
+
+It's recommended for newcomers to go this way. Various FPGA boards are supported
+and multiple examples provided! You can even run Linux on your FPGA using LiteX
+very easily!
+
+Migen documentation can be found here: https://m-labs.hk/migen/manual
+
+FPGA lessons/tutorials can be found at: https://github.com/enjoy-digital/fpga_101
+
+[> Medium Quick start guide with Conda
+-----------------------------------------
+
+0. Get miniconda by following instructions at https://conda.io/miniconda.html
+
+1. Clone LiteX
+ git clone --recurse-submodules https://github.com/enjoy-digital/litex.git
+
+2. Create a LiteX environment from environment.yml
+ conda env create -f environment.yml
+
+3. Enter conda environment
+ conda activate litex
+
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
+
+
+[> Quick start guide (for advanced users)
+-----------------------------------------
+0. Install Python 3.5+ and FPGA vendor's development tools.
+
+1. Get litex_setup.py script and execute:
+ ./litex_setup.py init install
+ This will clone and install Migen, LiteX and LiteX's cores.
+ To update all repositories execute:
+ ./litex_setup.py update
+
+2. Compile and install binutils. Take the latest version from GNU.
+ mkdir build && cd build
+ ../configure --target=lm32-elf
+ make
+ make install
+
+3. (Optional, only if you want to use a lm32 CPU in you SoC)
+ Compile and install GCC. Take gcc-core and gcc-g++ from GNU
+ (version 4.5 or >=4.9).
+ rm -rf libstdc++-v3
+ mkdir build && cd build
+ ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
+ --disable-libssp
+ make
+ make install
+
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
+
+5. ... and/or install Verilator and test LiteX on your computer:
+ Download and install Verilator: http://www.veripool.org/
+ Install libevent-devel / json-c-devel packages
+ Go to boards/targets
+ ./sim.py
+
+6. Run a terminal program on the board's serial port at 115200 8-N-1.
+ You should get the BIOS prompt.
+
+[> Contact
+----------
+E-mail: florent [AT] enjoy-digital.fr
projects / litex.git / blobdiff