---------------------------------------------------------------------------------
- __ _ __ _______ _________
- / / (_) /____ / __/ _ /_ __/ _ |
- / /__/ / __/ -_)\ \/ __ |/ / / __ |
- /____/_/\__/\__/___/_/ |_/_/ /_/ |_|
-
- Copyright 2014-2015 / Florent Kermarrec / florent@enjoy-digital.fr
-
- A lite open-source SATA1/2/3 controller
- developed in partnership with M-Labs Ltd / HKU
---------------------------------------------------------------------------------
-
-[> Getting started
-------------------
-1. Install Python3 and Xilinx's Vivado software.
-
-2. Obtain Migen and install it:
- git clone https://github.com/enjoy-digital/migen
- cd migen
- python3 setup.py install
- cd ..
-
-3. Obtain Miscope and install it:
- git clone https://github.com/enjoy-digital/miscope
- cd miscope
- python3 setup.py install
- cd ..
-
-4. Obtain MiSoC:
- git clone https://github.com/enjoy-digital/misoc --recursive
-
-5. Copy lite-sata in working directory and move to it.
-
-6. Build and load design:
- make all
-
-7. Test design:
- go to test directory
- python3 bist.py
-
-[> Simulations :
- Simulation are avalaible in ./lib/sata/test:
- - crc_tb
- - scrambler_tb
- - phy_datapath_tb
- - link_tb
- - command_tb
- - bist_tb
- hdd.py is a HDD model with implementing all SATA layers.
- To run a simulation, move to the simulation directory and run:
- make simulation_name
-
-[> Tests :
- A synthetisable BIST is provided. It can be controled with ./test/bist.py
+ __ _ __ _ __
+ / / (_) /____ | |/_/
+ / /__/ / __/ -_)> <
+ /____/_/\__/\__/_/|_|
+ Migen inside
+
+ Build your hardware, easily!
+ Copyright 2012-2015 Enjoy-Digital
+
+[> Intro
+---------
+LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
+our cores, integrate them in complete SoC and load/flash them to the hardware.
+
+The structure of LiteX is kept close to MiSoC to ease collaboration between
+projects and efforts are made to keep cores developed with LiteX compatible
+with MiSoC (user will only need to import new modules introduced by LiteX).
+
+LiteX is based on Migen.
+
+[> License
+-----------
+LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
+Since it is based on MiSoC, please also refer to LICENSE file in soc directory
+or git history to get correct copyrights.
+
+[> Sub-packages
+----------------
+gen:
+ Provides specific or experimentatl modules to generate HDL that are not integrated
+ in Migen.
+
+build:
+ Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
+ simulate HDL code or full SoCs.
+
+soc:
+ Provides definitions/modules to build cores (bus, bank, flow), cores and tools
+ to build a SoC from such cores.
+
+boards:
+ Provides platforms and targets for the supported boards.
+
+[> Quick start guide
+--------------------
+0. If cloned from Git without the --recursive option, get the submodules:
+ git submodule update --init
+
+1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
+ Get Migen from: https://github.com/m-labs/migen
+
+2. Compile and install binutils. Take the latest version from GNU.
+ mkdir build && cd build
+ ../configure --target=lm32-elf
+ make
+ make install
+
+3. (Optional, only if you want to use a lm32 CPU in you SoC)
+ Compile and install GCC. Take gcc-core and gcc-g++ from GNU
+ (version 4.5 or >=4.9).
+ rm -rf libstdc++-v3
+ mkdir build && cd build
+ ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
+ --disable-libssp
+ make
+ make install
+
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
+
+5. ... and/or install Verilator and test LiteX on your computer:
+ Download and install Verilator: http://www.veripool.org/
+ Go to boards/targets
+ ./sim.py
+
+6. Run a terminal program on the board's serial port at 115200 8-N-1.
+ You should get the BIOS prompt.
[> Contact
-E-mail: florent@enjoy-digital.fr
+E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file
projects / litex.git / blobdiff