gen/fhdl/verilog: remove asic_syntax and expose reg_initialization, dummy_signal...

[litex.git] / README

diff --git a/README b/README
index 3f792aab6d4a10a29f6e75e13ceb3149e0283aa0..646283f7d7510426b38327f22717678e2b8df436 100644 (file)
--- a/README
+++ b/README
@@ -5,7 +5,7 @@
                          Migen inside
 
                 Build your hardware, easily!
-                Copyright 2015 Enjoy-Digital
+             Copyright 2012-2015 Enjoy-Digital
 
 [> Intro
 ---------
@@ -13,13 +13,14 @@ LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
 our cores, integrate them in complete SoC and load/flash them to the hardware.
 
 The structure of LiteX is kept close to MiSoC to ease collaboration between 
-projects.
+projects and efforts are made to keep cores developed with LiteX compatible
+with MiSoC (user will only need to import new modules introduced by LiteX).
 
 LiteX is based on Migen.
 
 [> License
 -----------
-LiteX is copyright (c) 2015 Enjoy-Digital under BSD Lisense.
+LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
 Since it is based on MiSoC, please also refer to LICENSE file in soc directory
 or git history to get correct copyrights.
 
@@ -45,7 +46,8 @@ boards:
 0. If cloned from Git without the --recursive option, get the submodules:
   git submodule update --init
 
-1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
+1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
+  Get Migen from: https://github.com/m-labs/migen
 
 2. Compile and install binutils. Take the latest version from GNU.
   mkdir build && cd build