Migen inside
Build your hardware, easily!
- Copyright 2012-2016 Enjoy-Digital
+ Copyright 2012-2017 Enjoy-Digital
[> Intro
----------
+--------
LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
to build our cores, integrate them in complete SoC and load/flash them to
the hardware and experiment new features.
compatible with Migen/MiSoC.
[> License
------------
-LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
+----------
+LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
directory or git history to get correct copyrights.
[> Sub-packages
-----------------
+---------------
gen:
- Provides specific or experimentatl modules to generate HDL that are not integrated
+ Provides specific or experimental modules to generate HDL that are not integrated
in Migen.
build:
0. If cloned from Git without the --recursive option, get the submodules:
git submodule update --init
-1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
- Get Migen from: https://github.com/m-labs/migen
+1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
2. Compile and install binutils. Take the latest version from GNU.
mkdir build && cd build
5. ... and/or install Verilator and test LiteX on your computer:
Download and install Verilator: http://www.veripool.org/
+ Install libevent-devel / json-c-devel packages
Go to boards/targets
./sim.py
You should get the BIOS prompt.
[> Contact
+----------
E-mail: florent [AT] enjoy-digital.fr
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