Merge pull request #36 from mattkelly/fix-readme-typo

[litex.git] / README

diff --git a/README b/README
index a9b608fa4415cdc5012c8eda83fdb14595d6cb8b..6f4affa2723e09e6d0e668839caa6f74028c2b0e 100644 (file)
--- a/README
+++ b/README
@@ -5,28 +5,28 @@
                          Migen inside
 
                 Build your hardware, easily!
-             Copyright 2012-2015 Enjoy-Digital
+             Copyright 2012-2017 Enjoy-Digital
 
 [> Intro
----------
-LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build 
-our cores, integrate them in complete SoC and load/flash them to the hardware.
+--------
+LiteX is an alternative to Migen/MiSoC maintained and used by Enjoy-Digital
+to build our cores, integrate them in complete SoC and load/flash them to
+the hardware and experiment new features.
 
-The structure of LiteX is kept close to MiSoC to ease collaboration between 
-projects.
-
-LiteX is based on Migen.
+The structure of LiteX is kept close to Migen/MiSoC to ease collaboration
+between projects and efforts are made to keep cores developed with LiteX
+compatible with Migen/MiSoC.
 
 [> License
------------
-LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
-Since it is based on MiSoC, please also refer to LICENSE file in soc directory
-or git history to get correct copyrights.
+----------
+LiteX is Copyright (c) 2012-2017 Enjoy-Digital under BSD Lisense.
+Since it is based on Migen/MiSoC, please also refer to LICENSE file in gen/soc
+directory or git history to get correct copyrights.
 
 [> Sub-packages
-----------------
+---------------
 gen:
-  Provides specific or experimentatl modules to generate HDL that are not integrated
+  Provides specific or experimental modules to generate HDL that are not integrated
   in Migen.
 
 build:
@@ -45,8 +45,7 @@ boards:
 0. If cloned from Git without the --recursive option, get the submodules:
   git submodule update --init
 
-1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
-  Get Migen from: https://github.com/m-labs/migen
+1. Install Python 3.3+ and FPGA vendor's development tools and JTAG tools.
 
 2. Compile and install binutils. Take the latest version from GNU.
   mkdir build && cd build
@@ -69,6 +68,7 @@ boards:
 
 5. ... and/or install Verilator and test LiteX on your computer:
   Download and install Verilator: http://www.veripool.org/
+  Install libevent-devel / json-c-devel packages
   Go to boards/targets
   ./sim.py
 
@@ -76,4 +76,5 @@ boards:
   You should get the BIOS prompt.
 
 [> Contact
+----------
 E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file