- __ _ __ ______ __
- / / (_) /____ / __/ /_/ /
- / /__/ / __/ -_) _// __/ _ \
- /____/_/\__/\__/___/\__/_//_/
+ __ _ __ _ __
+ / / (_) /____ | |/_/
+ / /__/ / __/ -_)> <
+ /____/_/\__/\__/_/|_|
+ Migen inside
- Copyright 2012-2015 / EnjoyDigital
- florent@enjoy-digital.fr
-
- A small footprint and configurable Ethernet core
- developed by EnjoyDigital
-
-[> Doc
----------
-HTML : www.enjoy-digital.fr/litex/liteeth/
-PDF : www.enjoy-digital.fr/litex/liteeth.pdf
+ Build your hardware, easily!
+ Copyright 2012-2015 Enjoy-Digital
[> Intro
---------
-LiteEth provides a small footprint and configurable Ethernet core.
-
-LiteEth is part of LiteX libraries whose aims are to lower entry level of
-complex FPGA IP cores by providing simple, elegant and efficient implementations
-ofcomponents used in today's SoC such as Ethernet, SATA, PCIe, SDRAM Controller...
+LiteX is an alternative to MiSoC maintained and used by Enjoy-Digital to build
+our cores, integrate them in complete SoC and load/flash them to the hardware.
-The core uses simple and specific streaming buses and will provides in the future
-adapters to use standardized AXI or Avalon-ST streaming buses.
+The structure of LiteX is kept close to MiSoC to ease collaboration between
+projects.
-Since Python is used to describe the HDL, the core is highly and easily
-configurable.
-
-LiteEth uses technologies developed in partnership with M-Labs Ltd:
- - Migen enables generating HDL with Python in an efficient way.
- - MiSoC provides the basic blocks to build a powerful and small footprint SoC.
-
-LiteEth can be used as a Migen/MiSoC library (by simply installing it
-with the provided setup.py) or can be integrated with your standard design flow
-by generating the verilog rtl that you will use as a standard core.
-
-[> Features
------------
-- Ethernet MAC with various interfaces and various PHYs (GMII, MII, Loopback)
-- Hardware UDP/IP stack with ARP and ICMP
-
-[> Possibles improvements
--------------------------
-- add standardized interfaces (AXI, Avalon-ST)
-- add DMA interface to MAC
-- add hardware Etherbone support
-- add RGMII/SGMII PHYs
-- ... See below Support and Consulting :)
-
-If you want to support these features, please contact us at florent [AT]
-enjoy-digital.fr. You can also contact our partner on the public mailing list
-devel [AT] lists.m-labs.hk.
-
-
-[> Getting started
-------------------
-1. Install Python3 and Xilinx's Vivado software
-
-2. Obtain Migen and install it:
-(we use EnjoyDigital fork for now until new features are merged
-into upstream Migen)
- git clone https://github.com/enjoy-digital/migen
- cd migen
- python3 setup.py install
- cd ..
-
-3. Obtain LiteScope and install it:
- git clone https://github.com/enjoy-digital/litescope
- cd litescope
- python3 setup.py install
- cd ..
-
-4. Obtain MiSoC:
- git clone https://github.com/m-labs/misoc --recursive
- XXX add setup.py to MiSoC for external use of misoclib?
-
-5. Obtain LiteEth
- git clone https://github.com/enjoy-digital/liteeth
-
-6. Build and load UDP loopback design (only for KC705 for now):
- python3 make.py all (-s UDPSoCDevel to add LiteScopeLA)
-
-7. Test design (only for KC705 for now):
- go to ./test directory and run:
- change com port in config.py to your com port
- try to ping 192.168.1.40
- python3 test_udp.py
-
-[> Simulations:
- Simulations are available in ./liteth/test/:
- - mac_core_tb
- - mac_wishbone_tb
- - arp_tb
- - ip_tb
- - icmp_tb
- - udp_tb
- All ethernet layers have their own model tested against real Ethernet dumps (dumps.py)
- To run a simulation, move to ./liteeth/test and run:
- make simulation_name
-
-[> Tests :
- An UDP loopback is provided and be controlled with: /test/test_udp.py
+LiteX is based on Migen.
[> License
-----------
-LiteEth is released under the very permissive two-clause BSD license. Under
-the terms of this license, you are authorized to use LiteEth for closed-source
-proprietary designs.
-Even though we do not require you to do so, those things are awesome, so please
-do them if possible:
- - tell us that you are using LiteEth
- - cite LiteEth in publications related to research it has helped
- - send us feedback and suggestions for improvements
- - send us bug reports when something goes wrong
- - send us the modifications and improvements you have done to LiteEth.
-
-[> Support and Consulting
---------------------------
-We love open-source hardware and like sharing our designs with others.
-
-LiteEth is developed and maintained by EnjoyDigital.
-
-If you would like to know more about LiteEth or if you are already a happy
-user and would like to extend it for your needs, EnjoyDigital can provide standard
-commercial support as well as consulting services.
-
-So feel free to contact us, we'd love to work with you! (and eventually shorten
-the list of the possible improvements :)
+LiteX is Copyright (c) 2012-2015 Enjoy-Digital under BSD Lisense.
+Since it is based on MiSoC, please also refer to LICENSE file in soc directory
+or git history to get correct copyrights.
+
+[> Sub-packages
+----------------
+gen:
+ Provides specific or experimentatl modules to generate HDL that are not integrated
+ in Migen.
+
+build:
+ Provides tools to build FPGA bitstreams (interface to vendor toolchains) and to
+ simulate HDL code or full SoCs.
+
+soc:
+ Provides definitions/modules to build cores (bus, bank, flow), cores and tools
+ to build a SoC from such cores.
+
+boards:
+ Provides platforms and targets for the supported boards.
+
+[> Quick start guide
+--------------------
+0. If cloned from Git without the --recursive option, get the submodules:
+ git submodule update --init
+
+1. Install Python 3.3+, Migen and FPGA vendor's development tools and JTAG tools.
+ Get Migen from: https://github.com/m-labs/migen
+
+2. Compile and install binutils. Take the latest version from GNU.
+ mkdir build && cd build
+ ../configure --target=lm32-elf
+ make
+ make install
+
+3. (Optional, only if you want to use a lm32 CPU in you SoC)
+ Compile and install GCC. Take gcc-core and gcc-g++ from GNU
+ (version 4.5 or >=4.9).
+ rm -rf libstdc++-v3
+ mkdir build && cd build
+ ../configure --target=lm32-elf --enable-languages="c,c++" --disable-libgcc \
+ --disable-libssp
+ make
+ make install
+
+4. Build the target of your board...:
+ Go to boards/targets and execute the target you want to build
+
+5. ... and/or install Verilator and test LiteX on your computer:
+ Download and install Verilator: http://www.veripool.org/
+ Go to boards/targets
+ ./sim.py
+
+6. Run a terminal program on the board's serial port at 115200 8-N-1.
+ You should get the BIOS prompt.
[> Contact
E-mail: florent [AT] enjoy-digital.fr
\ No newline at end of file