add better debug logs and asserts for SelectableInt slice

[openpower-isa.git] / README.md

diff --git a/README.md b/README.md
index ccb33539db54c9b9be832649a964e71fc86c1d93..708b81e2d4fb1f91e9311dc9ef58fcb12ad09e6a 100644 (file)
--- a/README.md
+++ b/README.md
@@ -25,6 +25,7 @@ Once those are sorted, installation and setup is as follows:
 * python3 setup.py develop
 * make svanalysis
 * make pywriter
+* make pyfnwriter
 
 # Usage
 
@@ -82,7 +83,17 @@ cartoons especially appreciated:
 
 All programs are written by Libre-SOC team members are LGPLv3+.
 However the specification and the CSV files came from their
-respective Copyright holders (IBM, OpenPOWER Foundation, Microwatt)
+respective Copyright holders (IBM, OpenPOWER Foundation, Microwatt).
+
+Bear in mind that the *facts* in a specification may not be copyrighted,
+however the document (or source code) *containing* those facts can be and
+is copyrightable.  In this repository, the **facts** were extracted
+(from Microwatt and from the OpenPOWER ISA Technical Specification).
+
+Therefore, you, likewise, may *also* extract the **facts** from this
+source code, but for the actual source code itself you must respect the
+terms and conditions of the LGPLv3+ License in which those facts happen
+to be embedded.
 
 # Other Unit Tests