framebuffer: disable debugger by default

[litex.git] / build.py

diff --git a/build.py b/build.py
index aaf9c569d2ecfee7bec3b979c81926e0304758f6..9907effbaf78f30572a036bdefa2b5cc52ad82c6 100644 (file)
--- a/build.py
+++ b/build.py
@@ -12,6 +12,7 @@ def add_core_dir(d):
 def add_core_files(d, files):
        for f in files:
                verilog_sources.append(os.path.join("verilog", d, f))
+add_core_dir("generic")
 add_core_dir("m1crg")
 add_core_dir("s6ddrphy")
 add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
@@ -20,8 +21,8 @@ add_core_files("lm32", ["lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v
        "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
        "lm32_dcache.v", "lm32_top.v", "lm32_debug.v", "lm32_jtag.v", "jtag_cores.v",
        "jtag_tap_spartan6.v"])
+add_core_dir("minimac3")
 
-os.system("rm -rf build/*")
 os.chdir("build")
 
 def str2file(filename, contents):
@@ -35,33 +36,8 @@ str2file("soc.v", src_verilog)
 str2file("soc.ucf", src_ucf)
 verilog_sources.append("build/soc.v")
 
-#raise SystemExit
-
-# xst
+# generate XST project file
 xst_prj = ""
 for s in verilog_sources:
        xst_prj += "verilog work ../" + s + "\n"
 str2file("soc.prj", xst_prj)
-str2file("soc.xst", """run
--ifn soc.prj
--top soc
--ifmt MIXED
--opt_mode SPEED
--opt_level 2
--resource_sharing no
--reduce_control_sets auto
--ofn soc.ngc
--p xc6slx45-fgg484-2""")
-os.system("xst -ifn soc.xst")
-
-# ngdbuild
-os.system("ngdbuild -uc soc.ucf soc.ngc")
-
-# map
-os.system("map -ol high -w soc.ngd")
-
-# par
-os.system("par -ol high -w soc.ncd soc-routed.ncd")
-
-# bitgen
-os.system("bitgen -g Binary:Yes -g INIT_9K:Yes -w soc-routed.ncd soc.bit")