Merge branch 'master' of ssh://git.libre-riscv.org:922/ls2

[ls2.git] / coldboot / coldboot.c

diff --git a/coldboot/coldboot.c b/coldboot/coldboot.c
index 6c7b8cccd20db70dc318c8875906aebed78f2b55..86318ddc4634633fd923dbae3012f96aa232f33e 100644 (file)
--- a/coldboot/coldboot.c
+++ b/coldboot/coldboot.c
@@ -92,47 +92,8 @@ void isr(void) {
 
 }
 
-// WARNING
-// KESTREL SPECIFIC
-#define TERCEL_SPI_REG_SYS_PHY_CFG1     0x10
-#define TERCEL_SPI_REG_SYS_FLASH_CFG5       0x24
-#define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK   0xff
-#define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT  0
-#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK   0x1
-#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT  0
-static inline uint32_t read_tercel_register(uint8_t reg)
-{
-       return readl((unsigned long)(SPI_FCTRL_BASE+reg));
-}
-
-static inline void write_tercel_register(uint8_t reg, uint32_t value)
-{
-       writel(value, (unsigned long)(SPI_FCTRL_BASE+reg));
-}
-
-// TODO: need to use this
-// https://gitlab.raptorengineering.com/kestrel-collaboration/kestrel-firmware/bare-metal-firmware/-/blob/master/main.c#L2328
-
-/* this is a "level 1" speed-up, which gets an initial improvement of 10-50x
- * over the default speed (which is a scant 100 bytes per second).
- */
-static void crank_up_qspi_level1(void)
-{
-    // WARNING: KESTREL SPECIFIC
-    // Set SPI clock cycle divider to 1
-    uint32_t dword;
-    dword = read_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1);
-    dword &= ~(TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK <<
-               TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
-    dword |= ((1 & TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK) <<
-                   TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT);
-    write_tercel_register(TERCEL_SPI_REG_SYS_PHY_CFG1, dword);
-    // Enable read merging
-    dword = read_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5);
-    dword |= (TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK <<
-              TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT);
-    write_tercel_register(TERCEL_SPI_REG_SYS_FLASH_CFG5, dword);
-}
+extern void crank_up_qspi_level1(void);
+extern int host_spi_flash_init(void);
 
 static bool fl_read(void *dst, uint32_t offset, uint32_t size)
 {
@@ -268,9 +229,6 @@ int main(void) {
     puts("\r\n");
 
     if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
-        // speed up the QSPI to at least a sane level
-        crank_up_qspi_level1();
-
         puts("SPI Offset: ");
         spi_offs = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
         uart_writeuint32(spi_offs);
@@ -299,13 +257,24 @@ int main(void) {
         //volatile uint8_t *qspi_bytes = (uint8_t*)spi_offs;
          // let's not, eh? writel(0xDEAF0123, (unsigned long)&(qspi[0]));
          // tmp = readl((unsigned long)&(qspi[0]));
-        for (int i=0;i<2;i++) {
+        for (int i=0;i<10;i++) {
           tmp = readl((unsigned long)&(qspi[i]));
           uart_writeuint32(tmp);
           puts(" ");
           if ((i & 0x7) == 0x7) puts("\r\n");
         }
         puts("\r\n");
+
+        // speed up the QSPI to at least a sane level
+        crank_up_qspi_level1();
+        // run at saner level
+        host_spi_flash_init();
+
+        puts("SPI Offset: ");
+        spi_offs = readl(SYSCON_BASE + SYS_REG_SPI_INFO);
+        uart_writeuint32(spi_offs);
+        puts("\r\n");
+
         /*
         for (i=0;i<256;i++) {
           tmp = readb((unsigned long)&(qspi_bytes[i]));
@@ -555,7 +524,8 @@ int main(void) {
         volatile uint32_t *mem = (uint32_t*)0x1000000;
         fl_read(mem,       // destination in RAM
                 0x600000,  // offset into QSPI
-                0x1000000); // length - shorter (testing) 0x8000); 
+                0x8000); // length - shorter (testing) 0x8000);
+                //0x1000000); // length 
         puts("dump mem\n");
         for (int i=0;i<256;i++) {
           tmp = readl((unsigned long)&(mem[i]));