}
int main(void) {
- const int kNumIterations = 65536;
+ const int kNumIterations = 14;
int res, failcnt = 0;
uint32_t tmp;
volatile uint32_t *ram = DRAM_BASE;
console_init();
- puts("Firmware launched...\n");
+ //puts("Firmware launched...\n");
+
+ puts("fw..");
+#if 1
+ volatile uint32_t *hyperram = 0xa0000000;
+ // quick write/read
+ writel(0xDEAF0000, (unsigned long)&(hyperram[0]));
+ tmp = readl((unsigned long)&(hyperram[0]));
+ puts("read ");
+ uart_writeuint32(tmp);
+
+ return 0;
+#endif
puts("DRAM init... ");
+
struct gramCtx ctx;
struct gramProfile profile = {
.mode_registers = {
0x320, 0x6, 0x200, 0x0
},
- .rdly_p0 = 2,
- .rdly_p1 = 2,
+ .rdly_p0 = 5,
+ .rdly_p1 = 5,
};
struct gramProfile profile2;
gram_init(&ctx, &profile, (void*)DRAM_BASE, //0x10000000,
(void*)DRAM_INIT_BASE); //0x00008000);
puts("done\n");
+#if 1
puts("Rdly\np0: ");
for (size_t i = 0; i < 8; i++) {
profile2.rdly_p0 = i;
gram_load_calibration(&ctx, &profile2);
- puts("loaded ");
gram_reset_burstdet(&ctx);
- puts("burstreset ");
+
for (size_t j = 0; j < 128; j++) {
- tmp = readl((unsigned long)&ram[i]);
+ tmp = readl((unsigned long)&(ram[i]));
}
if (gram_read_burstdet(&ctx, 0)) {
puts("1");
for (size_t i = 0; i < 8; i++) {
profile2.rdly_p1 = i;
gram_load_calibration(&ctx, &profile2);
- puts("loaded ");
gram_reset_burstdet(&ctx);
- puts("burstreset ");
for (size_t j = 0; j < 128; j++) {
- tmp = readl((unsigned long)&ram[i]);
+ tmp = readl((unsigned long)&(ram[i]));
}
if (gram_read_burstdet(&ctx, 1)) {
puts("1");
}
puts("done\n");
+#endif
+
puts("Auto calibration profile:");
puts("p0 rdly:");
uart_writeuint32(profile2.rdly_p0);
puts("DRAM test... \n");
for (size_t i = 0; i < kNumIterations; i++) {
- ram[i] = 0xDEAF0000 | i*4;
+ writel(0xDEAF0000 | i*4, (unsigned long)&(ram[i]));
}
- for (size_t i = 0; i < kNumIterations; i++) {
- if (ram[i] != (0xDEAF0000 | i*4)) {
- puts("fail : *(0x");
- uart_writeuint32(&ram[i]);
- puts(") = ");
- uart_writeuint32(ram[i]);
- putchar('\n');
- failcnt++;
-
- if (failcnt > 10) {
- puts("Test canceled (more than 10 errors)\n");
- break;
- }
- }
- }
+ for (int dly = 0; dly < 8; dly++) {
+ failcnt = 0;
+ profile2.rdly_p0 = dly;
+ profile2.rdly_p1 = dly;
+ puts("p0 rdly:");
+ uart_writeuint32(profile2.rdly_p0);
+ puts(" p1 rdly:");
+ uart_writeuint32(profile2.rdly_p1);
+ gram_load_calibration(&ctx, &profile2);
+ for (size_t i = 0; i < kNumIterations; i++) {
+ if (readl((unsigned long)&(ram[i])) != (0xDEAF0000 | i*4)) {
+ puts("fail : *(0x");
+ uart_writeuint32(&ram[i]);
+ puts(") = ");
+ uart_writeuint32(ram[i]);
+ puts("\n");
+ failcnt++;
+
+ if (failcnt > 10) {
+ puts("Test canceled (more than 10 errors)\n");
+ break;
+ }
+ }
+ }
+ }
puts("done\n");
- while (1);
-
return 0;
}