Merge branch 'master' of ssh://git.libre-riscv.org:922/ls2

[ls2.git] / coldboot / tercel_spi.h

diff --git a/coldboot/tercel_spi.h b/coldboot/tercel_spi.h
new file mode 100644 (file)
index 0000000..bd4a9d5
--- /dev/null
+++ b/coldboot/tercel_spi.h
@@ -0,0 +1,68 @@
+// © 2020 Raptor Engineering, LLC
+//
+// Released under the terms of the GPL v3
+// See the LICENSE file for full details
+
+#define TERCEL_SPI_REG_DEVICE_ID_HIGH 0x0
+#define TERCEL_SPI_REG_DEVICE_ID_LOW  0x4
+#define TERCEL_SPI_REG_DEVICE_VERSION 0x8
+#define TERCEL_SPI_REG_SYS_CLK_FREQ   0xc
+#define TERCEL_SPI_REG_SYS_PHY_CFG1   0x10
+#define TERCEL_SPI_REG_SYS_FLASH_CFG1 0x14
+#define TERCEL_SPI_REG_SYS_FLASH_CFG2 0x18
+#define TERCEL_SPI_REG_SYS_FLASH_CFG3 0x1c
+#define TERCEL_SPI_REG_SYS_FLASH_CFG4 0x20
+#define TERCEL_SPI_REG_SYS_FLASH_CFG5 0x24
+#define TERCEL_SPI_REG_SYS_CORE_CTL1  0x28
+#define TERCEL_SPI_REG_SYS_CORE_DATA1 0x2c
+
+#define TERCEL_SPI_DEVICE_ID_HIGH 0x7c525054
+#define TERCEL_SPI_DEVICE_ID_LOW  0x5350494d
+
+#define TERCEL_SPI_VERSION_MAJOR_MASK  0xffff
+#define TERCEL_SPI_VERSION_MAJOR_SHIFT 16
+#define TERCEL_SPI_VERSION_MINOR_MASK  0xff
+#define TERCEL_SPI_VERSION_MINOR_SHIFT 8
+#define TERCEL_SPI_VERSION_PATCH_MASK  0xff
+#define TERCEL_SPI_VERSION_PATCH_SHIFT 0
+
+#define TERCEL_SPI_ENABLE_USER_MODE_MASK        0x1
+#define TERCEL_SPI_ENABLE_USER_MODE_SHIFT       0x0
+#define TERCEL_SPI_PHY_DUMMY_CYCLES_MASK        0xff
+#define TERCEL_SPI_PHY_DUMMY_CYCLES_SHIFT       8
+#define TERCEL_SPI_PHY_CLOCK_DIVISOR_MASK       0xff
+#define TERCEL_SPI_PHY_CLOCK_DIVISOR_SHIFT      0
+#define TERCEL_SPI_PHY_IO_TYPE_MASK             0x3
+#define TERCEL_SPI_PHY_IO_TYPE_SHIFT            16
+#define TERCEL_SPI_PHY_4BA_ENABLE_MASK          0x1
+#define TERCEL_SPI_PHY_4BA_ENABLE_SHIFT         18
+#define TERCEL_SPI_PHY_FAST_READ_ENABLE_MASK    0x1
+#define TERCEL_SPI_PHY_FAST_READ_ENABLE_SHIFT   19
+#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_MASK    0x1
+#define TERCEL_SPI_PHY_QSPI_EXT_READ_EN_SHIFT   20
+#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_MASK   0x1
+#define TERCEL_SPI_PHY_QSPI_EXT_WRITE_EN_SHIFT  21
+#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_MASK   0xff
+#define TERCEL_SPI_PHY_CS_EXTRA_IDLE_CYC_SHIFT  24
+#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_MASK  0x1
+#define TERCEL_SPI_FLASH_EN_MULTCYC_WRITE_SHIFT 1
+#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_MASK   0x1
+#define TERCEL_SPI_FLASH_EN_MULTCYC_READ_SHIFT  0
+#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_MASK   0xffffffff
+#define TERCEL_SPI_FLASH_CS_EN_LIMIT_CYC_SHIFT  0
+
+#define TERCEL_SPI_3BA_SPI_CMD_MASK   0xff
+#define TERCEL_SPI_3BA_SPI_CMD_SHIFT  0
+#define TERCEL_SPI_4BA_SPI_CMD_MASK   0xff
+#define TERCEL_SPI_4BA_SPI_CMD_SHIFT  8
+#define TERCEL_SPI_3BA_QSPI_CMD_MASK  0xff
+#define TERCEL_SPI_3BA_QSPI_CMD_SHIFT 16
+#define TERCEL_SPI_4BA_QSPI_CMD_MASK  0xff
+#define TERCEL_SPI_4BA_QSPI_CMD_SHIFT 24
+
+#define TERCEL_SPI_PHY_IO_TYPE_SINGLE 0x0
+#define TERCEL_SPI_PHY_IO_TYPE_QUAD   0x2
+
+#define TERCEL_SPI_PHY_3BA_MODE 0x0
+#define TERCEL_SPI_PHY_4BA_MODE 0x1
+