framebuffer: fake DMA for testing (WIP)

[litex.git] / constraints.py

diff --git a/constraints.py b/constraints.py
index 1214a60beb1d6ca3807c8c3e89a27b3297aa6aa4..4e2c4f7c4802226318f05e26157394e5f772e272 100644 (file)
--- a/constraints.py
+++ b/constraints.py
@@ -1,5 +1,5 @@
 class Constraints:
-       def __init__(self, crg0, norflash0, uart0, ddrphy0):
+       def __init__(self, crg0, norflash0, uart0, ddrphy0, minimac0, fb0):
                self.constraints = []
                def add(signal, pin, vec=-1, iostandard="LVCMOS33", extra=""):
                        self.constraints.append((signal, vec, pin, iostandard, extra))
@@ -15,6 +15,8 @@ class Constraints:
                add(crg0.videoin_rst_n, "W17")
                add(crg0.flash_rst_n, "P22", extra="SLEW = FAST | DRIVE = 8")
                add(crg0.trigger_reset, "AA4")
+               add(crg0.phy_clk, "M20")
+               add(crg0.vga_clk_pad, "A11")
                
                add_vec(norflash0.adr, ["L22", "L20", "K22", "K21", "J19", "H20", "F22",
                        "F21", "K17", "J17", "E22", "E20", "H18", "H19", "F20",
@@ -47,6 +49,28 @@ class Constraints:
                        extra=ddrsettings)
                add_vec(ddrphy0.sd_dm, ["E1", "E3", "F3", "G4"], extra=ddrsettings)
                add_vec(ddrphy0.sd_dqs, ["F1", "F2", "H5", "H6"], extra=ddrsettings)
+               
+               add(minimac0.phy_rst_n, "R22")
+               add(minimac0.phy_dv, "V21")
+               add(minimac0.phy_rx_clk, "H22")
+               add(minimac0.phy_rx_er, "V22")
+               add_vec(minimac0.phy_rx_data, ["U22", "U20", "T22", "T21"])
+               add(minimac0.phy_tx_en, "N19")
+               add(minimac0.phy_tx_clk, "H21")
+               add(minimac0.phy_tx_er, "M19")
+               add_vec(minimac0.phy_tx_data, ["M16", "L15", "P19", "P20"])
+               add(minimac0.phy_col, "W20")
+               add(minimac0.phy_crs, "W22")
+               
+               add_vec(fb0.vga_r, ["C6", "B6", "A6", "C7", "A7", "B8", "A8", "D9"])
+               add_vec(fb0.vga_g, ["C8", "C9", "A9", "D7", "D8", "D10", "C10", "B10"])
+               add_vec(fb0.vga_b, ["D11", "C12", "B12", "A12", "C13", "A13", "D14", "C14"])
+               add(fb0.vga_hsync_n, "A14")
+               add(fb0.vga_vsync_n, "C15")
+               add(fb0.vga_psave_n, "B14")
+               
+               self._phy_rx_clk = minimac0.phy_rx_clk
+               self._phy_tx_clk = minimac0.phy_tx_clk
 
        def get_ios(self):
                return set([c[0] for c in self.constraints])
@@ -69,6 +93,18 @@ INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 
 PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
-"""
+
+NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
+NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
+TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
+TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
+TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
+TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
+
+NET "asfifo*/counter_read/gray_count*" TIG;
+NET "asfifo*/counter_write/gray_count*" TIG;
+NET "asfifo*/preset_empty*" TIG;
+
+""".format(phy_rx_clk=ns.get_name(self._phy_rx_clk), phy_tx_clk=ns.get_name(self._phy_tx_clk))
        
                return r