framebuffer: fake DMA for testing (WIP)

[litex.git] / constraints.py

diff --git a/constraints.py b/constraints.py
index 75fafc14808e9a34a959886c47516aac862f89ec..4e2c4f7c4802226318f05e26157394e5f772e272 100644 (file)
--- a/constraints.py
+++ b/constraints.py
@@ -100,6 +100,11 @@ TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
 TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
 TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
 TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
+
+NET "asfifo*/counter_read/gray_count*" TIG;
+NET "asfifo*/counter_write/gray_count*" TIG;
+NET "asfifo*/preset_empty*" TIG;
+
 """.format(phy_rx_clk=ns.get_name(self._phy_rx_clk), phy_tx_clk=ns.get_name(self._phy_tx_clk))
        
                return r