Make the debug tests aware of multicore.

[riscv-tests.git] / debug / targets / RISC-V / spike32-2.py

diff --git a/debug/targets/RISC-V/spike32-2.py b/debug/targets/RISC-V/spike32-2.py
new file mode 100644 (file)
index 0000000..3f87d26
--- /dev/null
+++ b/debug/targets/RISC-V/spike32-2.py
@@ -0,0 +1,11 @@
+import targets
+import testlib
+
+import spike32
+
+class spike32_2(targets.Target):
+    harts = [spike32.spike32_hart(), spike32.spike32_hart()]
+    openocd_config_path = "spike.cfg"
+
+    def create(self):
+        return testlib.Spike(self)