Make the debug tests aware of multicore.

[riscv-tests.git] / debug / targets / RISC-V / spike64.py

diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
index c70585782622610b4513cbaedbff5fb1fc49af1d..84586e33f46d682d18ab63db92ec4b5c83562da5 100644 (file)
--- a/debug/targets/RISC-V/spike64.py
+++ b/debug/targets/RISC-V/spike64.py
@@ -1,12 +1,17 @@
 import targets
 import testlib
 
-class spike64(targets.Target):
+class spike64_hart(targets.Hart):
     xlen = 64
     ram = 0x1212340000
     ram_size = 0x10000000
     instruction_hardware_breakpoint_count = 4
     reset_vector = 0x1000
+    link_script_path = "spike64.lds"
+
+class spike64(targets.Target):
+    harts = [spike64_hart()]
+    openocd_config_path = "spike.cfg"
 
     def create(self):
         return testlib.Spike(self)