Really these should also be auto-generated. Testing through compiling
can now take place.
+## Compiling the BSV to verilog
+
+Here an additional repository is required, which can be cloned as follows:
+
+ $ git clone gitolite3@libre-riscv.org:shakti-iclass.git
+
+or public:
+
+ $ git clone git://libre-riscv.org/shakti-iclass.git
+
+This pulls in submodules automatically, and begins building the BSV,
+using the following commands:
+
+ $ ./bin/gitmoduleupdate.sh
+ $ make
+
+As the compilation of the soc can take some time, it is possible to use
+the Makefile.peripherals to compile *only* the slow\_peripherals.bsv
+file (which we did not do with the sdram case because sdram is a fast
+peripheral). This would be achieved with the following commands:
+
+ $ make spec_to_pinmux
+ $ make pinmux_to_bsv
+ $ cd build/i_class/bsv_src
+ $ make -f Makefile.peripherals gen_verilog
+
+## Summary
+
+This particular example has been something of a "cheat". The similarity
+between SD/MMC and eMMC is so high - the only differences being the name
+of the interface and the number of data pins - that it was simple and
+straightforward to re-use significant amounts of code, cut/paste style,
+carrying out some re-factoring where needed.
+
+It does however have the advantage of being quite a short tutorial, that
+illustrates key aspects of adding slow bus peripherals.
# Conclusion