Update copyright notices

[litex.git] / examples / basic_sim.py

diff --git a/examples/basic_sim.py b/examples/basic_sim.py
index 332881d3ab43f6acc0e679a27be9ae3ea1ae230a..af00d0df009238f2813f0993b6f236dbf111be99 100644 (file)
--- a/examples/basic_sim.py
+++ b/examples/basic_sim.py
@@ -1,19 +1,41 @@
+# Copyright (C) 2012 Vermeer Manufacturing Co.
+# License: GPLv3 with additional permissions (see README).
+
 from migen.fhdl.structure import *
 from migen.sim.generic import Simulator
 from migen.sim.icarus import Runner
 
+# Our simple counter, which increments at every cycle
+# and prints its current value in simulation.
 class Counter:
        def __init__(self):
                self.count = Signal(BV(4))
        
-       def do_simulation(self, s, cycle):
-               print("Cycle: " + str(cycle) + " Count: " + str(s.rd(self.count)))
+       # This function will be called at every cycle.
+       def do_simulation(self, s):
+               # Simply read the count signal and print it.
+               # The output is:
+               # Count: 0 
+               # Count: 1
+               # Count: 2
+               # ...
+               print("Count: " + str(s.rd(self.count)))
        
        def get_fragment(self):
+               # At each cycle, increase the value of the count signal.
+               # We do it with convertible/synthesizable FHDL code.
                sync = [self.count.eq(self.count + 1)]
+               # List our simulation function in the fragment.
                sim = [self.do_simulation]
                return Fragment(sync=sync, sim=sim)
 
-dut = Counter()
-sim = Simulator(dut.get_fragment(), Runner())
-sim.run(10)
+def main():
+       dut = Counter()
+       # Use the Icarus Verilog runner.
+       # We do not specify a top-level object, and use the default.
+       sim = Simulator(dut.get_fragment(), Runner())
+       # Since we do not use sim.interrupt, limit the simulation
+       # to some number of cycles.
+       sim.run(20)
+
+main()