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correctly set SR_EA bit for all vector physical tests
[riscv-tests.git] / isa / rv64uv / ld.S
diff --git a/isa/rv64uv/ld.S b/isa/rv64uv/ld.S
index a2f6b891d19bda5becd234b0e4cbd97fa8869990..354ee38531f87e329acb5b3da19e8e83ba5cb0d6 100644 (file)
--- a/isa/rv64uv/ld.S
+++ b/isa/rv64uv/ld.S
@@ -8,7 +8,7 @@
 #include "riscv_test.h"
 #include "test_macros.h"
 
-RVTEST_RV64U
+RVTEST_RV64UV
 RVTEST_CODE_BEGIN
 
   vsetcfg 16,0