etherbone: cleanup

[litex.git] / liteeth / core / etherbone / wishbone.py

diff --git a/liteeth/core/etherbone/wishbone.py b/liteeth/core/etherbone/wishbone.py
index 50cd175dabfe74acd48cdd47c8fc251ad8dd2930..d49e43410f989106aba56c65f98faed980000699 100644 (file)
--- a/liteeth/core/etherbone/wishbone.py
+++ b/liteeth/core/etherbone/wishbone.py
@@ -3,47 +3,44 @@ from migen.bus import wishbone
 
 class LiteEthEtherboneWishboneMaster(Module):
        def __init__(self):
-               self.wr_sink = wr_sink = Sink(eth_etherbone_mmap_description(32))
-               self.rd_sink = rd_sink = Sink(eth_etherbone_mmap_description(32))
-               self.wr_source = wr_source = Source(eth_etherbone_mmap_description(32))
-               self.rd_source = rd_source = Source(eth_etherbone_mmap_description(32))
+               self.sink = sink = Sink(eth_etherbone_mmap_description(32))
+               self.source = source = Source(eth_etherbone_mmap_description(32))
                self.bus = bus = wishbone.Interface()
                ###s
 
-               data = FlipFlop(32)
-               self.submodules += data
+               self.submodules.data = data = FlipFlop(32)
                self.comb += data.d.eq(bus.dat_r)
 
                self.submodules.fsm = fsm = FSM(reset_state="IDLE")
                fsm.act("IDLE",
-                       wr_sink.ack.eq(1),
-                       rd_sink.ack.eq(1),
-                       If(wr_sink.stb & wr_sink.sop,
-                               wr_sink.ack.eq(0),
-                               NextState("WRITE_DATA")
-                       ).Elif(rd_sink.stb & rd_sink.sop,
-                               rd_sink.ack.eq(0),
-                               NextState("READ_DATA")
+                       sink.ack.eq(1),
+                       If(sink.stb & sink.sop,
+                               sink.ack.eq(0),
+                               If(sink.we,
+                                       NextState("WRITE_DATA")
+                               ).Else(
+                                       NextState("READ_DATA")
+                               )
                        )
                )
                fsm.act("WRITE_DATA",
-                       bus.adr.eq(wr_sink.addr),
-                       bus.dat_w.eq(wr_sink.data),
-                       bus.sel.eq(wr_sink.be),
-                       bus.stb.eq(wr_sink.stb),
+                       bus.adr.eq(sink.addr),
+                       bus.dat_w.eq(sink.data),
+                       bus.sel.eq(sink.be),
+                       bus.stb.eq(sink.stb),
                        bus.we.eq(1),
                        bus.cyc.eq(1),
                        If(bus.stb & bus.ack,
-                               wr_sink.ack.eq(1),
-                               If(wr_sink.eop,
+                               sink.ack.eq(1),
+                               If(sink.eop,
                                        NextState("IDLE")
                                )
                        )
                )
                fsm.act("READ_DATA",
-                       bus.adr.eq(rd_sink.addr),
-                       bus.sel.eq(rd_sink.be),
-                       bus.stb.eq(rd_sink.stb),
+                       bus.adr.eq(sink.addr),
+                       bus.sel.eq(sink.be),
+                       bus.stb.eq(sink.stb),
                        bus.cyc.eq(1),
                        If(bus.stb & bus.ack,
                                data.ce.eq(1),
@@ -51,17 +48,18 @@ class LiteEthEtherboneWishboneMaster(Module):
                        )
                )
                fsm.act("SEND_DATA",
-                       wr_source.stb.eq(rd_sink.stb),
-                       wr_source.sop.eq(rd_sink.sop),
-                       wr_source.eop.eq(rd_sink.eop),
-                       wr_source.base_addr.eq(rd_sink.base_addr),
-                       wr_source.addr.eq(rd_sink.addr),
-                       wr_source.count.eq(rd_sink.count),
-                       wr_source.be.eq(rd_sink.be),
-                       wr_source.data.eq(data.q),
-                       If(wr_source.stb & wr_source.ack,
-                               rd_sink.ack.eq(1),
-                               If(wr_source.eop,
+                       source.stb.eq(sink.stb),
+                       source.sop.eq(sink.sop),
+                       source.eop.eq(sink.eop),
+                       source.base_addr.eq(sink.base_addr),
+                       source.addr.eq(sink.addr),
+                       source.count.eq(sink.count),
+                       source.be.eq(sink.be),
+                       source.we.eq(1),
+                       source.data.eq(data.q),
+                       If(source.stb & source.ack,
+                               sink.ack.eq(1),
+                               If(source.eop,
                                        NextState("IDLE")
                                ).Else(
                                        NextState("READ_DATA")